SPRZ444C February 2018 – November 2026 DRA780 , DRA781 , DRA782 , DRA783 , DRA786 , DRA787
System I2C Hang Due to Miss of Bus Clear Support
Low
There is no H/W mechanism preventing violating below I2C Bus clear standard requirement.
If the data line (SDA) is stuck LOW, the master should send 9 clock pulses. The device that held the bus LOW should release it sometime within those 9 clocks. If not, then use the HW reset or cycle power to clear the bus.
Sys_Warmreset doesn't reset the I2C IP it does at IC level.
So, once the situation is reached, IC is seeing bus busy status bit.
I2C SW handler could be programmed to detect such a locked situation. In this case, it will check the Bus Busy bit and issue the needed clock pulses.
SR 2.0A, 2.0
TDA3x: 2.0A, 2.0, 1.0A, 1.0
DRA78x: 2.0A, 2.0
DM50x: 2.0