Details

Two package terminals will be assigned new signal functions as the device transitions from Silicon Revision 1.0 (SR1.0) to Silicon Revision 2.0 (SR2.0).

• J15
  • SR1.0: Assigned to VDDS_MMC0 (MMC0 PHY IO supply). ADC0_REFP is internally connected to VDDA_ADC0
  • SR2.0: Assigned to ADC0_REFP (ADC0 positive reference).
• J16
  • SR1.0: Assigned to VSS (Ground). ADC0_REFN is internally connected to VSS
  • SR2.0: Assigned to ADC0_REFN (ADC Negative Reference)

• When installing SR2.0 device on existing SR1.0 designed boards
  • For boards with VDDA_ADC0 and VDDS_MMC0 connected to the same power supply
    • An SR2.0 device may experience reduced ADC0 performance
      • This can occur because ADC0_REFP will be connected to the VDDS_MMC0 digital supply which will couple noise directly into ADC0 reference.
  • For boards with VDDA_ADC0 and VDDS_MMC0 connected to different power supplies
    • Potential applied to VDDS_MMC0 must never exceed the potential applied to VDDA_ADC0.
      • This condition of operation is required because the new SR2.0 pin assignment connects ADC0_REFP to the VDDS_MMC0 digital power supply and the internal ESD protection circuit associated with ADC0_REFP is referenced to VDDA_ADC0, which may be sourced from a separate analog power supply. This requires the potential applied to ADC0_REFP to be less than or equal to potential applied to VDDA_ADC0. This power sequencing requirement for ADC0_REFP relative to VDDA_ADC0 is passed along to VDDS_MMC0 when a SR2.0 device is installed on a PCB previously designed for a SR1.0 device. Therefore, it is important to confirm this condition of operation is not violated during power-up and power-down when VDDS_MMC0 and VDDA_ADC0 are sourced from different power supplies.
    • If ADC0 is not being used, where VDDA_ADC0 is connected to VSS as described in the Connections for Unused Pins section of the datasheet, a SR2.0 device cannot be installed
      • This is not allowed because the potential applied to ADC0_REFP can never exceed the potential applied to VDDA_ADC0, and ADC0_REFP will be connected to VDDS_MMC0 when a SR2.0 device is installed on a PCB previously designed for a SR1.0 device.
• New board design which will support both SR1.0 and SR2.0 devices
  • Place a zero ohm resistor on the back-side of the PCB, under the BGA array, connected between J13 and J15.
    • When SR1.0 is installed, do not populate this resistor
    • When SR2.0 is installed, populate this resistor.
  • An additional high-frequency de-coupling capacitor should be placed on the back-side of the PCB, under the BGA array, connected between J15 and J16.
  • Connect J16 directly to VSS power plane
• New board design which will only support SR2.0 devices
  • Connect J13 to J15
  • Connect J16 directly to VSS power plane
  • An additional high-frequency de-coupling capacitor should be placed on the back-side of the PCB, under the BGA array, connected between J15 and J16.
  • See Note