SPRZ457H January   2021  – December 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

 

  1.   1
  2. 1Usage Notes and Advisories Matrices
    1. 1.1 Devices Supported
  3. 2Silicon Usage Notes and Advisories
    1. 2.1 Silicon Usage Notes
      1.      i2287
      2.      i2351
    2. 2.2 Silicon Advisories
      1.      i2049
      2.      i2062
      3.      i2103
      4.      i2184
      5.      i2189
      6.      i2236
      7.      i2185
      8.      i2196
      9.      i2207
      10.      i2208
      11.      i2228
      12.      i2232
      13.      i2244
      14.      i2245
      15.      i2091
      16.      i2235
      17.      i2303
      18.      i2317
      19.      i2134
      20.      i2257
      21.      i2277
      22.      i2285
      23.      i2310
      24.      i2311
      25.      i2313
      26.      i2328
      27.      i2241
      28.      i2279
      29.      i2307
      30.      i2320
      31.      i2329
      32.      i2331
      33.      i2243
      34.      i2249
      35.      i2256
      36.      i2274
      37.      i2278
      38.      i2306
      39.      i2363
      40.      i2312
      41.      i2371
      42.      i2366
      43.      i2138
      44.      i2253
      45.      i2259
      46.      i2283
      47.      i2305
      48.      i2326
      49.      i2368
      50.      i2383
      51.      i2401
      52.      i2409
  4.   Trademarks
  5.   Revision History

i2285

BCDMA: Blockcopy Gets Corrupted if TR Read Responses Interleave with Source Data Fetch

Details

BCDMA can get corrupted during a block copy operation if the 64B TR descriptor fetch goes to an endpoint that can fragment the 64B burst into smaller burst sizes. This includes DDR where the read transaction will be fragmented to 32B bursts. The only endpoint where fragmentation won't happen is the 2MB OCSRAM. Corruption occurs if the first 32B of the descriptor fetch is returned and the second 32B of the descriptor fetch is delayed such that the BCDMA starts fetching source data and starts receiving that data before the second 32B is received by the BCDMA.

Workaround

BCDMA block-copy TR descriptors have to be placed in the 2MB OCSRAM. Alternatively the block-copy TR descriptors may be placed in DDR with the requirement that the block copy source data must also be in DDR. Refer to the table below for details.

Table 2-1
Module Endpoint Size Could be used for pktDMA descriptors or TR Could it be used for data buffer for pktDMA( source data or dest data) Could be used for BCDMA descriptors or TR BCDMA split TX/RX channel any considerations on BCDMA source data Can be used as BCDMA block copy dest data? PG2.0 Considerations
DDR up to 2GB Yes Yes Yes Yes. Limited to DDR size per TR. no additional TR storage restriction. Limit to DDR size per TR, and TR for this channel should stored in DDR Yes, no additional considerations Yes. Limited to DDR size per TR. No additional TR storage restriction.
main R5 TCM single core mode 64KB ATCM+64KB BTCM. Dual core mode 32KB ATCM+32KB BTCM. No Yes No Yes, no additional TR storage restriction. Not to be used as BCDMA's source data Yes, no additional considerations Yes, no additional TR storage restriction.
main domain on-chip SRAM 8 banks of memory, each bank is 256KB Yes Yes Yes Limit to aligned 256KB per TR, can not cross 256KB boundary within the same TR. No additional TR storage considerations. Limit to aligned 256KB per TR, can not cross 256KB boundary within the same TR. And TR and the source data needs to be in the same memory bank. Yes, no additional considerations Limit to aligned 256KB per TR. No additional TR storage requirement.
1KB PSRAM in main_infra 1KB, used for boot vector storage. Not for TR No Yes No Limit to aligned 64KB per TR. No additional TR storage considerations. Not to be used as BCDMA's source data Yes, no additional considerations Yes, limited to DMSC_lite memory size (64KB_64KB). no additional TR storage restriction.
DMSC_lite SRAM 64KB+64KB Yes Yes Yes Yes, no additional TR storage restriction. Limit to the DMSC_lite memory size (64KB+64KB) per TR. And TR has to be stored in the same memory end point. Yes, no additional considerations Yes, limited to DMSC_lite memory size (64KB_64KB). No additional TR storage restriction.
OSPI flash Up to 4GB No Yes No Yes, no additional TR storage restriction. Not to be used as BCDMA's source data Yes, no additional considerations Yes. Limit to flash size. no additional TR storage restriction.
GPMC up to 128MB No Yes No Yes, no additional TR storage restriction. Not to be used as BCDMA's source data Yes, no additional considerations Yes. no additional TR storage restriction.
PCIe Up to 4GB Yes, but Linux does not support this use case Yes Yes, but Linux does not support this use case Yes, no additional TR storage restriction. The descriptor for Block copy has to be stored on the remote side. Not possible for Linux usecase. Yes, no additional considerations Yes. no additional TR storage restriction.
ROM No Yes, only as source data No Only split RX channel. No additional TR storage restriction. Not to be used as BCDMA's source data No, ROM only supports read. Yes. no additional TR storage restriction.