SWRZ150A December   2024  – October 2025 AWR2544

 

  1.   1
  2. 1Introduction
  3. 2Device Nomenclature
  4. 3Device Markings
  5. 4Advisory to Silicon Variant / Revision Map
  6. 5Known Design Exceptions to Functional Specifications
    1.     MSS#25
    2.     MSS#27
    3.     MSS#28
    4.     MSS#29
    5.     MSS#30
    6.     MSS#33
    7.     MSS#40
    8. 5.1  MSS#49
    9. 5.2  MSS#52
    10. 5.3  MSS#53
    11. 5.4  MSS#54
    12. 5.5  MSS#55
    13. 5.6  MSS#56
    14. 5.7  MSS#57
    15. 5.8  MSS#58
    16. 5.9  MSS#59
    17. 5.10 MSS#60
    18. 5.11 MSS#61
    19. 5.12 MSS#62
    20. 5.13 MSS#63
    21. 5.14 MSS#64
    22. 5.15 MSS#65
    23.     MSS#68
    24.     MSS#71
    25. 5.16 ANA#12A
    26.     ANA#37A
    27.     ANA#39
    28.     ANA#43
    29.     ANA#44
    30.     ANA#45
    31.     ANA#47
    32.     ANA#59
  7.   Trademarks
  8. 6Revision History

ANA#44

In 3.3V IO mode, back power is observed on the 1.8V rail from 3.3V rail

Revision(s) Affected:

AWR2544

Description:

When the 3.3V power rail comes up and 1.8V has not been supplied yet, there is a voltage rise seen on the 1.8V VIOIN rail due to the leakage path within the IO cell.

Workaround(s):

It is recommended to use the following workarounds:

  1. Use appropriate Supply Sequencing: Supply 1.8V first and then 3.3V.
  2. In case the PMIC fails to powerup due to sensing an existing voltage at its output, this voltage detection scheme in the PMIC should be disabled.