Revision(s) Affected:

AWR2544

Description:

A potential L2 cache corruption issue during block coherence operations has been identified. Under a specific set of circumstances, L1D or L2 block coherence operations can cause L2 cache corruption. The problem arises when the following four actions happen back to back in the same L2 set:

1. L1D write miss

2. Victim writeback due to block coherence operations

3. Write allocate for some address

4. Read or write allocate for some address

This issue applies to all the block coherence operations listed below:

• L1D writeback

• L1D invalidate

• L1D writeback with invalidate

• L2 writeback

• L2 invalidate

• L2 writeback with invalidate

Workaround(s):

The workaround requires that the memory system be idle during the block coherence operations. Hence programs must wait for block coherence operations to complete before continuing. This applies to L1D and L2 memory block coherence operations. To issue a block coherence operation follow the sequence below.

1. Disable interrupts.

2. Write the starting address to the corresponding BAR register.

3. Write the word count to the corresponding WC register.

4. Wait for completion by one of the following methods:

   1. Issue an MFENCE instruction (preferred).

   2. Poll the WC register until the word count field reads as 0.

5. Perform 16 NOPs.

6. Restore interrupts.

For further information about the cache control registers (BAR and WC) see the TMS320C66x DSP CorePac User Guide (SPRUGW0). The MFENCE instruction is new to the C66x DSP. It stalls the DSP until all outstanding memory operations complete. For further information about the MFENCE instruction, see the C66x DSP and Instruction Set Reference Guide (SPRUGH7).