SWRZ150A December   2024  – October 2025 AWR2544

 

  1.   1
  2. 1Introduction
  3. 2Device Nomenclature
  4. 3Device Markings
  5. 4Advisory to Silicon Variant / Revision Map
  6. 5Known Design Exceptions to Functional Specifications
    1.     MSS#25
    2.     MSS#27
    3.     MSS#28
    4.     MSS#29
    5.     MSS#30
    6.     MSS#33
    7.     MSS#40
    8. 5.1  MSS#49
    9. 5.2  MSS#52
    10. 5.3  MSS#53
    11. 5.4  MSS#54
    12. 5.5  MSS#55
    13. 5.6  MSS#56
    14. 5.7  MSS#57
    15. 5.8  MSS#58
    16. 5.9  MSS#59
    17. 5.10 MSS#60
    18. 5.11 MSS#61
    19. 5.12 MSS#62
    20. 5.13 MSS#63
    21. 5.14 MSS#64
    22. 5.15 MSS#65
    23.     MSS#68
    24.     MSS#71
    25. 5.16 ANA#12A
    26.     ANA#37A
    27.     ANA#39
    28.     ANA#43
    29.     ANA#44
    30.     ANA#45
    31.     ANA#47
    32.     ANA#59
  7.   Trademarks
  8. 6Revision History

4 Advisory to Silicon Variant / Revision Map

Table 4-1 Silicon Variant / Revision Map
ADVISORY NUMBERADVISORY TITLEAWR2544
MAIN SUBSYSTEM

MSS#25

Debugger May Display Unpredictable Data in the Memory Browser Window if a System Reset OccursX

MSS#27

MibSPI in Peripheral Mode in 3- or 4-Pin Communication Transmits Data Incorrectly for Slow SPICLK Frequencies and for Clock Phase = 1X

MSS#28

A Data Length Error is Generated Repeatedly in Peripheral Mode When IO Loopback is EnabledX

MSS#29

Spurious RX DMA REQ From a Peripheral Mode MibSPIX

MSS#30

MibSPI RX RAM RXEMPTY Bit Does Not Get Cleared After ReadingX

MSS#33

MibSPI RAM ECC is Not Read Correctly in DIAG ModeX

MSS#40

Any EDMA Transfer That Spans ACCEL_MEM1 +ACCEL_MEM2 Memories of Hardware Accelerator May Result In Data Corruption Without Any Notification Of Error From The SoCX

MSS#49

Issues seen in potential interoperability with receiver supporting only Strict Alignment User Flow Control Stripping during Overflow message transmission in Aurora 64B/66B ProtocolX

MSS#52

DSS L2 Parity Issue: When DSP sends out an access beyond configured memory sizeX

MSS#53

Incorrect behavior seen when context switch happens in the last parameter-set in HWA 2.0

X

MSS#54

Aurora TX UDP size<=4 is invalidX

MSS#55

PMIC CLKOUT dithering in chirp-to-chirp staircase mode not supportedX

MSS#56

CR4 STC Boot Monitor Failure

X

MSS#57

Loss of data observed on Flush/Marker or completion of packet over MDO interface.X

MSS#58

ePWM: Glitch during Chopper mode of operationX

MSS#59

CRC: CRC 8-bit data width and CRC8-SAE-J1850 and CRC8-H2F possible use in CAN module is not supportedX

MSS#60

Mismatch in Read and Write address for 6-internal registers of PCR

X

MSS#61

Data aborts seen while access made to last 24 bytes of the configured MPU region and cache is enabledX

MSS#62

HWA hangs when using back to back FFT3X paramsets

X

MSS#63

Potential L2 Cache Corruption During Block Coherence operations issue

X

MSS#64

Single MFENCE Issue

X

MSS#65

L2 Cache Corruption during block and global coherence operations issue

X

MSS#68

Potential corruption in FFT data for 0th BCNT in Real2X FFT Mode in HWA

X

MSS#71

Single bit ECC (error correction) mechanism can cause an incorrect memory update

X

ANALOG / MILLIMETER WAVE
ANA#12ASecond Harmonic (HD2) Present in the ReceiverX
ANA#37AHigh RX gain droop across LO frequencyX
ANA#39HPF cutoff frequency 2800kHz configuration can result in incorrect RX IFA gains and filter corner frequenciesX
ANA#43Errors seen in Synthesizer Frequency Live monitorX
ANA#44In 3.3V IO mode, back power is observed on the 1.8V rail from 3.3V railX
ANA#45Spurs Caused due to Digital ActivityX
ANA#47RX Spurs observed across RXs in Idle Channel ScenarioX
ANA#59Spurs caused due to OSC_CLK_OUT_ETH activityX