Revision(s) Affected:

AWR2544

Description:

Under a specific set of circumstances, L1D or L2 block and global coherence operations can cause L2 cache corruption. The problem arises when the following four actions happen back-to-back in the same L2 set:

1. L1D write miss
2. Invalidate or writeback-with-invalidate due to block and global coherence operations
3. Write allocate for some address
4. Read or write allocate for some address

This issue applies to all the block and global coherence operations EXCEPT:

• L1D block writeback
• L1D global writeback
• L2 block writeback
• L2 global writeback

See also: Advisory 63 - Potential L2 Cache Corruption During Block Coherence Operations Issue

Workaround(s):

Generic Workaround:

The workarounds below are very generic and may have performance impacts. Customers are requested to understand the application and see which one suits them better.

Workaround #1:

This workaround requires that the memory system be idle during the block and global coherence operations. Hence programs must wait for block and global coherence operations to complete before continuing. This applies to L1D and L2 memory block and global coherence operations.

To issue a block coherence operation, follow the sequence below:

1. Disable interrupts.

2. Write the starting address to the corresponding BAR register.

3. Write the word count to the corresponding WC register

4. Wait for completion by one of the following methods:

   1. Issue an MFENCE instruction (preferred)

   2. Poll the WC register until the word count field reads as 0

5. Perform 16 NOPs

6. Restore interrupts

To issue a global coherence operation, follow the sequence below:

1. Disable interrupts.

2. Write 1 to the corresponding global coherence register (L1DINV, L1DWBINV, L2DINV, and L2DWBINV)

3. Wait for completion by one of the following methods

   1. Issue an MFENCE instruction (preferred)

   2. Poll the corresponding global coherence register (L1DINV, L1DWBINV, L2DINV, and L2DWBINV) until the bit [0] field reads as 0

4. Perform 16 NOPs

5. Restore interrupts

Workaround #2:

This workaround is also generic, but will allow CPU traffic to go on in parallel with cache coherence operations. To issue a block coherence operation, follow the sequence below:

1. Issue a MFENCE command.

2. Freeze L1D cache

3. Start L1D WBINV

4. Restart CPU traffic (CPU operations happen in parallel with WBINV and do not need to wait for cache coherency operation to complete)

5. Poll the WC register until the word count field reads as 0.

6. WBINV completes when word count field reads 0

7. Issue an MFENCE command.

8. Unfreeze L1D cache.

For more information about the cache control registers (BAR, WC, L1DINV, L1DWBINV, L2DINV, and L2DWBINV) see the TMS320C66x DSP CorePac User Guide (SPRUGW0). The MFENCE instruction is new to the C66x DSP. It stalls the DSP until all outstanding memory operations complete. For further information about the MFENCE instruction, see the C66x DSP and Instruction Set Reference Guide (SPRUGH7).