TIDT435 February 2025
Considering the converter is working in synchronous rectification status, the light load efficiency is very low. There are two options we can adopt to optimize the efficiency. One option is decreasing the switching frequency or adopting burst mode and another option is adjustable dead time. Of course, we also can combine the two options into one.
Table 2-9 lists the difference between Frequency Reduction Mode and Hysteretic Burst Mode.
Frequency reduction mode | Hysteretic burst mode | |
Principle | Continuously switches, reduce effective duty cycle while maintaining a minimum on-time | When Vcomp becomes <Vburst_threshold, the FETs stops switching |
Transient response | Reduced control loop bandwidth | Fast |
CPU utilization | Large, need to compute required FSW | Small, enable/disable switching based on comparator |
Output ripple | Small | Larger compared to FR mode |
Figure 2-13 to Figure 2-15 show the waveforms with or without optimization. CH1 is Vgs of secondary FET, CH2 is Vds of secondary FET, CH3 is voltage of transformer primary winding, CH4 is current of transformer primary winding.
With no optimization, the efficiency is only 80.05% when Vin is 600V, Vout is 9V with 20A output current. With hysteretic burst mode, the efficiency rises to 82.46%. With frequency reduction mode, the efficiency is 87.88%, making the best performance.
Similar as PSFB topology, lag bridge of SHB topology is challenging to achieve ZVS. To optimize efficiency, dead time must be optimized to achieve valley switching. As shown in Figure 2-16 to Figure 2-18, when output current is low, like 20A, this takes a longer time on Coss charging, so valley switching is usually with longer deadtime. When output current is high, like 120A, this takes a shorter time on Coss charging, so valley switching is usually with shorter deadtime.
Notice: When output current is low, ZVS can be achieved. Deadtime must not be too long, otherwise Coss oscillates with Ls.