TIDUF89 September   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Detection Theory
    2. 1.2 Multi-Pass Architecture
  8. 2System Overview
    1. 2.1 System Design Theory
      1. 2.1.1 Long Detection Range
        1. 2.1.1.1 Antenna Design for Long Detection Range
        2. 2.1.1.2 SNR Compensation for Long Detection Range
        3. 2.1.1.3 Smart Detection Logic
      2. 2.1.2 Low Power Consumption
        1. 2.1.2.1 Efficient Chirp Design
        2. 2.1.2.2 Deep Sleep Power Modes
        3. 2.1.2.3 Hardware Accelerator
      3. 2.1.3 Low False Alarm Rate
        1. 2.1.3.1 Typical Causes of False Alarms
        2. 2.1.3.2 False Alarms Outside the Detection Zone
        3. 2.1.3.3 False Alarms Within the Detection Zone
        4. 2.1.3.4 Adaptive State Machine
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Software Requirements
    3. 3.3 Test Setup
      1. 3.3.1 Test 1 - Detection Range
      2. 3.3.2 Test 2 - False Alarm Rate
      3. 3.3.3 Test 3 - Power Consumption
    4. 3.4 Test Results
  10. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
  11. 5Tools and Software
  12. 6Document Support
  13. 7Support Resources
  14. 8Trademarks
  15. 9About the Authors

2.1.2.3 Hardware Accelerator

The hardware accelerator on the IWRL6432AOP enables ultra-efficient computation of the most important operations needed for radar signal processing, which include windowing, FFT, Log-Mag and CFAR vector operations. Using the HWA decreases computation time significantly, allowing the radar sensor to spend more time in the deep sleep mode and less time in computation. Because the HWA uses streaming input and output, the number of cycles required for a sequence of FFTs is (1+NumFFT) * FFTSize, which is much faster than a typical O(NlogN) implementation. To illustrate some typical computation times for the IWRL6432AOP, Radar Hardware Accelerator, user's guide (Table 5) has been modified for the 80MHz HWA clock as shown in Table 2-3.

Table 2-3 FFT Computation Time (80MHz HWA Clock)
Example FFT Size Number of Back-to-Back Iterations Number of Clock Cycles (Initial Latency + Computation) Total Duration (assuming 80MHz clock)
1 256 4 256+ (256 × 4) 16 μsec
2 128 4 128 + (128 × 4) 8 μsec
3 8 64 8 + (8 × 64) 6.5 μsec