TIDUFD0 August   2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Wireless Hardware Configurations
      2. 2.2.2 Auxiliary Power Strategy
      3. 2.2.3 Thermistor Multiplexer
      4. 2.2.4 Cell Balancing
    3. 2.3 Highlighted Products
      1. 2.3.1 CC2662R-Q1
      2. 2.3.2 BQ78706
      3. 2.3.3 TMUX1308
      4. 2.3.4 LM5168
      5. 2.3.5 TMP61
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Software Requirements
    3. 3.3 Test Setup
    4. 3.4 Test Results
      1. 3.4.1 Network Performance
        1. 3.4.1.1 Network Initiation
        2. 3.4.1.2 Network Latency
        3. 3.4.1.3 PDR, PS
        4. 3.4.1.4 Low-Power Mode
      2. 3.4.2 Cell Voltage Accuracy
      3. 3.4.3 Temperature Sensing Using TMP61
      4. 3.4.4 Thermistor Multiplexer Timing
      5. 3.4.5 Current Consumption
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
      3. 4.1.3 Layout Prints
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author

3.4.1.2 Network Latency

This design tests the latency of a host microcontroller sending commands to WM responding to the data. This includes the latencies involved in the UART interface between the host microcontroller and the WM node and the wBMS communication frame between WM and WD nodes.

The BQ78706 receives read/write commands from the host microcontroller forwarded by the WM node. The WM node broadcasts (or unicasts) the request to one or more WD nodes, which forward the command to the BQ78706. The BQ78706 processes the request and returns a response wrapped in a packet with data specific to each WD node. Each WD node receives the response from the BQ78706 and transmits the response back to the WM node. Delivering the request from the host microcontroller to the WM node and getting a response back typically takes 1–2 wBMS communication frames. The frame period depends on the number of WD nodes and the network configurations.

  • The best case is 1 frame, if the WM node receives the host command right before frame starts
  • The worst case is 2 frames, if the WM node receives the host command after the frame starts, as the WM node needs to wait for the next frame
  • If there is a retransmission, then an extra frame needs to be added

The parameters in Table 3-5 are used for the latency tests.

Table 3-5 Network Configurations
ATTRIBUTE LENGTH (B) DATA DESCRIPTION
networkID 2 0xDDDD Network ID for the network
numULSlots 1 0x08 Number of devices in the network
ulSlotTime 1 90 Uplink slot duration in units of 16μs
dlSlotTime 2 310 Downlink slot duration in units of 16μs
minPNWDevices 1 =numULSlots Minimum number of devices for Partial Network (PNW)
maxRetries 1 03 Maximum number of retries to send a data frame
keepAliveInt 1 17 Keep-alive interval
ul2dlTime 1 40 Uplink to downlink turn around time in units of 16μs
NumSkipRxInt(Reserved) 1 3 Number of skipped keep-alive intervals
DenyList 5 0xFFFFFFFF Deny list of channel hopping sequence. Note: Make sure the number of data channels is ≥ 15

To test the latency, a broadcast voltage and GPIO read command with 168 bytes payload is sent from the serial port tool every 100ms. 168B bytes can include 52s cell voltage data and 8 GPIOs voltage data that are connected to the output of the thermistor multiplexer. The UART baud rate is 921600 bit/s.

Figure 3-2 shows the result without retransmission. The tested total latency is 39.2ms which means the WM node received the command after the frame started. The theoretical shortest length is 24.1ms.

TIDA-010976 168B Reading Latency Without Retransmission Figure 3-2 168B Reading Latency Without Retransmission

To reliably deliver a packet, WM node retransmits a packet if the node does not receive an acknowledgment (ack) from the WD nodes. Figure 3-3 shows the result with 3 retransmissions. The tested total latency is 88ms which means the WM node received the command after the frame started. The theoretical shortest length is 72.9ms. Even with 3 retransmissions, the 416s cell voltage and 64 GPIO reading interval is less than 100ms.

TIDA-010976 168B Reading Latency With 3 Retransmissions Figure 3-3 168B Reading Latency With 3 Retransmissions

If more GPIO voltages need to be read every 100ms, the uplink and downlink slot duration need be extended for robust wireless communication. See the configuring superframe and timing section in wBMS user guide.