TIDUFD0 August   2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Wireless Hardware Configurations
      2. 2.2.2 Auxiliary Power Strategy
      3. 2.2.3 Thermistor Multiplexer
      4. 2.2.4 Cell Balancing
    3. 2.3 Highlighted Products
      1. 2.3.1 CC2662R-Q1
      2. 2.3.2 BQ78706
      3. 2.3.3 TMUX1308
      4. 2.3.4 LM5168
      5. 2.3.5 TMP61
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Software Requirements
    3. 3.3 Test Setup
    4. 3.4 Test Results
      1. 3.4.1 Network Performance
        1. 3.4.1.1 Network Initiation
        2. 3.4.1.2 Network Latency
        3. 3.4.1.3 PDR, PS
        4. 3.4.1.4 Low-Power Mode
      2. 3.4.2 Cell Voltage Accuracy
      3. 3.4.3 Temperature Sensing Using TMP61
      4. 3.4.4 Thermistor Multiplexer Timing
      5. 3.4.5 Current Consumption
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
      3. 4.1.3 Layout Prints
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author

2.2.2 Auxiliary Power Strategy

Configure the #B0 AVDD as on to enable UART when #B0 is in shutdown mode. In theory, #B0 AVDD can be used to power the wBMS MCU, level shifter, and multiplexer but this configuration increases the current consumption of #B0. To avoid this, the design built an onboard power rail to power the wBMS MCU rather than use #B0 AVDD. Figure 2-4 shows the strategy for this design.

TIDA-010976 Auxiliary Power Strategy Figure 2-4 Auxiliary Power Strategy

The low-voltage ESS power strategy has a 120V input, 0.3A, ultra-low IQ synchronous buck DC/DC converter LM5168P with a low IQ 50mA LDO TPS71533 as the main power source, giving the system better efficiency and thermal performance than LDOs only.

A discrete step-down circuit is added before DC/DC because the 52s battery pack voltage can exceed 120V. Two NPN transistors are used in the step-down circuit to increase the DC current gain to lower the quiescent current. #B0 AVDD is connected to the output of DC/DC for redundancy. The CC2662R-Q1 is powered by #B0 AVDD if the LM5168 or step-down NPN circuit is failed. Set the LM5168 output voltage slightly above 5V, allowing the Schottky diodes to be reversed under normal operating conditions.

The auxiliary power rail can eliminate the current difference caused by the extra load on #B0 AVDD, but the power rail adds extra devices which create more complexity and cost. Figure 2-5 shows a low-cost alternative configuration.

TIDA-010976 Low-Cost Power Strategy Option Figure 2-5 Low-Cost Power Strategy Option

BQ78706 AVDD allows a maximum 20mA external load, so the CC2662R-Q1, which only requires about 10mA peak supply current, can be powered directly from the AVDD. Three dummy resistive loads, controlled by the BQ78706 GPIO, are added to balance the current consumption.