TIDUFE3 July   2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 TPS7A03
      2. 2.3.2 REF35
      3. 2.3.3 TVS3301
      4. 2.3.4 OPA391
      5. 2.3.5 AFE881H1
      6. 2.3.6 AFE882H1
      7. 2.3.7 SN74LV8T165
      8. 2.3.8 TMUX1219
  9. 3System Design Theory
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
    2. 4.2 Test Setup
    3. 4.3 Test Results
      1. 4.3.1 Linearity Tests
        1. 4.3.1.1 Linearity Tests Summary
      2. 4.3.2 Noise Tests and Current Histogram
        1. 4.3.2.1 Noise Tests and Current Histogram Summary
      3. 4.3.3 Step Response
        1. 4.3.3.1 Step Response Summary
      4. 4.3.4 Start-Up
      5. 4.3.5 MCU Current
        1. 4.3.5.1 MCU Current Summary
      6. 4.3.6 System Currents
        1. 4.3.6.1 Summary of System Currents
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
      3. 5.1.3 PCB Layout Recommendations
        1. 5.1.3.1 Layout Prints
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Author

2.3.7 SN74LV8T165

The SN74LV8T165 device is a parallel- or serial-in, serial-out 8-bit shift register. This device has two modes of operation: load data, and shift data which are controlled by the SH/LD input. The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example 3.3V to 2.5V output).