Product details

Technology Family ACT IOL (Max) (mA) 24 IOH (Max) (mA) -24 Operating temperature range (C) -40 to 85 Rating Catalog
Technology Family ACT IOL (Max) (mA) 24 IOH (Max) (mA) -24 Operating temperature range (C) -40 to 85 Rating Catalog
SSOP (DL) 56 191 mm² 18.42 x 10.35 TSSOP (DGG) 56 113 mm² 14 x 8.1
  • Members of the Texas Instruments WidebusTM Family
  • Inputs Are TTL-Voltage Compatible
  • 3-State True Outputs
  • Flow-Through Architecture Optimizes PCB Layout
  • Distributed VCC and GND Pin Configurations Minimize High-Speed Switching Noise
  • EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
  • 500-mA Typical Latch-Up Immunity at 125°C
  • Package Options Include Plastic Thin Shrink Small-Outline (DGG) and 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings, and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings

 

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

  • Members of the Texas Instruments WidebusTM Family
  • Inputs Are TTL-Voltage Compatible
  • 3-State True Outputs
  • Flow-Through Architecture Optimizes PCB Layout
  • Distributed VCC and GND Pin Configurations Minimize High-Speed Switching Noise
  • EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
  • 500-mA Typical Latch-Up Immunity at 125°C
  • Package Options Include Plastic Thin Shrink Small-Outline (DGG) and 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings, and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings

 

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

The 'ACT16543 are 16-bit registered transceivers that contain two sets of D-type latches for temporary storage of data flowing in either direction. The 'ACT16543 can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch enable ( or ) and output-enable ( or ) inputs are provided for each register to permit independent control in either direction of data flow.

The A-to-B enable () and inputs must be low to enter data from A or to output data to B. Having CEAB\ low and LEAB\ low makes the A-to-B latches transparent; a subsequent low-to-high transition at puts the A latches in the storage mode. Data flow from B to A is similar, but requires using the , , and inputs.

The 74ACT16543 is packaged in TI's shrink small-outline package, which provides twice the functionality of standard small-outline packages in the same printed-circuit-board area.

The 54ACT16543 is characterized for operation over the full military temperature range of -55°C to 125°C. The 74ACT16543 is characterized for operation from -40°C to 85°C.

 

The 'ACT16543 are 16-bit registered transceivers that contain two sets of D-type latches for temporary storage of data flowing in either direction. The 'ACT16543 can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch enable ( or ) and output-enable ( or ) inputs are provided for each register to permit independent control in either direction of data flow.

The A-to-B enable () and inputs must be low to enter data from A or to output data to B. Having CEAB\ low and LEAB\ low makes the A-to-B latches transparent; a subsequent low-to-high transition at puts the A latches in the storage mode. Data flow from B to A is similar, but requires using the , , and inputs.

The 74ACT16543 is packaged in TI's shrink small-outline package, which provides twice the functionality of standard small-outline packages in the same printed-circuit-board area.

The 54ACT16543 is characterized for operation over the full military temperature range of -55°C to 125°C. The 74ACT16543 is characterized for operation from -40°C to 85°C.

 

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Technical documentation

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Type Title Date
* Data sheet 16-Bit Registered Transceivers With 3-State Outputs datasheet (Rev. B) 01 Apr 1996
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

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SSOP (DL) 56 View options
TSSOP (DGG) 56 View options

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