Home Data converters Analog-to-digital converters (ADCs) High-speed ADCs (≥10 MSPS)
Home
Data converters
Analog-to-digital converters (ADCs)
High-speed ADCs (≥10 MSPS)

ADC09SJ1300

ACTIVE

Single-channel, 9-bit, 1.3-GSPS analog-to-digital converter (ADC) with JESD204C interface

Order now
Data sheet

ADC09SJ1300

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 1300 Resolution (Bits) 9 Number of input channels 1 Interface type JESD204B, JESD204C Analog input BW (MHz) 6000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 940 Architecture Folding Interpolating SNR (dB) 53.5 ENOB (bit) 8.5 SFDR (dB) 64 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 1300 Resolution (Bits) 9 Number of input channels 1 Interface type JESD204B, JESD204C Analog input BW (MHz) 6000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 940 Architecture Folding Interpolating SNR (dB) 53.5 ENOB (bit) 8.5 SFDR (dB) 64 Operating temperature range (°C) -40 to 85 Input buffer Yes
FCCSP (AAV) 144 100 mm² 10 x 10
  • ADC Core:
    • Resolution: 9 Bit
    • Maximum sampling rate: 1.3 GSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1 dBFS):
    • SNR (100 MHz): 53.5 dBFS
    • ENOB (100 MHz): 8.5 Bits
    • SFDR (100 MHz): 64 dBc
    • Noise floor (–20 dBFS): –143 dBFS
  • Full-scale input voltage: 800 mVPP-DIFF
  • Full-power input bandwidth: 6 GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
    • Maximum baud-rate: 17.16 Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2 GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (1 GSPS):
    • Quad Channel: 450 mW / channel
    • Dual channel: 625 mW / channel
    • Single channel: 940 mW
  • Power supplies: 1.1 V, 1.9 V
  • ADC Core:
    • Resolution: 9 Bit
    • Maximum sampling rate: 1.3 GSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1 dBFS):
    • SNR (100 MHz): 53.5 dBFS
    • ENOB (100 MHz): 8.5 Bits
    • SFDR (100 MHz): 64 dBc
    • Noise floor (–20 dBFS): –143 dBFS
  • Full-scale input voltage: 800 mVPP-DIFF
  • Full-power input bandwidth: 6 GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
    • Maximum baud-rate: 17.16 Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2 GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (1 GSPS):
    • Quad Channel: 450 mW / channel
    • Dual channel: 625 mW / channel
    • Single channel: 940 mW
  • Power supplies: 1.1 V, 1.9 V

ADC09xJ1300 is a family of quad, dual and single channel, 9-bit, 1.3 GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 9-bit resolution makes the ADC09xJ1300 ideally suited for suited for a variety of multi-channel communications and test systems.

Full-power input bandwidth (-3 dB) of 6 GHz enables direct RF sampling of of L-band and S-band.

ADC09xJ1300 is a family of quad, dual and single channel, 9-bit, 1.3 GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 9-bit resolution makes the ADC09xJ1300 ideally suited for suited for a variety of multi-channel communications and test systems.

Full-power input bandwidth (-3 dB) of 6 GHz enables direct RF sampling of of L-band and S-band.
open-in-new Find other High-speed ADCs (≥10 MSPS)
Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 1
Type Title Date
* Data sheet ADC09xJ1300 Quad, Dual, Single Channel, 1.3-GSPS, 9-bit Analog-to-Digital Converter (ADC) with JESD204C Interface datasheet PDF | HTML 19 Aug 2021

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADC09QJ1300EVM — ADC09QJ1300 evaluation module for quad-channel, 9-bit, 1.3-GSPS ADC with JESD204C interface

The ADC09QJ1300 evaluation module (EVM) allows for the evaluation of the ADC09QJ1300-Q1 device. ADC09QJ1300-Q1 is a low-power, 9-bit, quad-channel, 1.3-GSPS analog-to-digital converter (ADC) with a buffered analog input and integrated digital down converter with on-chip PLL, which features a (...)

User guide: PDF
Not available on TI.com
Evaluation board

TSW12QJ1600EVM — ADC12QJ1600-Q1 8-ch (two synchronized 4-ch) 12-bit 1.6-GSPS JESD204C interface ADC evaluation module

The TSW12QJ1600 evaluation module (EVM) is used to evaluate the ADC12QJ1600-Q1 analog-to-digital converter (ADC) with different front-end options. ADC12QJ1600-Q1 is a 12-bit ADC capable of operating at sampling rates up to 1.6 gigasample per second (GSPS) with four analog input channels.

This design (...)

User guide: PDF
Not available on TI.com
Simulation model

ADC12QJ1600 IBIS-AMI Model

SBAM512.ZIP (68 KB) - IBIS-AMI Model
Download
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Request
Package Pins Download
FCCSP (AAV) 144 View options
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos