ADS6125/ADS6124/ADS6123/ADS6122 (ADS612X) is a family of 12-bit A/D converters with sampling frequencies up to 125 MSPS. It combines high performance and low power consumption in a compact 32 QFN package. Using an internal high bandwidth sample and hold and a low jitter clock buffer helps to achieve high SNR and high SFDR even at high input frequencies.
It features coarse and fine gain options that are used to improve SFDR performance at lower full-scale analog input ranges.
The digital data outputs are either parallel CMOS or DDR LVDS (Double Data Rate). Several features exist to ease data capture such as — controls for output clock position and output buffer drive strength, and LVDS current and internal termination programmability.
The output interface type, gain, and other functions are programmed using a 3-wire serial interface. Alternatively, some of these functions are configured using dedicated parallel pins so that the device comes up in the desired state after power-up.
ADS612X includes internal references, while eliminating the traditional reference pins and associated external decoupling. External reference mode is also supported.
The devices are specified over the industrial temperature range (-40°C to 85°C).
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | 12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS and CMOS OUTPUTS datasheet (Rev. A) | 04 Dec 2007 | |
| Application note | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 22 May 2015 | ||
| Application note | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 19 Jul 2013 | ||
| Application note | Band-Pass Filter Design Techniques for High-Speed ADCs | 27 Feb 2012 | ||
| Application note | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 10 Sep 2010 | ||
| Application note | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 28 Apr 2009 | ||
| Application note | CDCE62005 as Clock Solution for High-Speed ADCs | 04 Sep 2008 | ||
| Application note | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 08 Jun 2008 | ||
| Application note | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 02 Jun 2008 | ||
| Application note | QFN Layout Guidelines | 28 Jul 2006 |
For additional terms or required resources, click any title below to view the detail page where available.
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| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| VQFN (RHB) | 32 | Ultra Librarian |
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Analog Engineer's Calc Installer
General calculator tool for analog design support.
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