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Data sheet
ADS61B23
- Maximum Sample Rate: 80 MSPS
- 12-bit Resolution with No Missing Codes
- Buffered Analog Inputs with
- Very Low Input Capacitance (< 2 pF)
- High DC Resistance (5 k
)
- 82 dBc SFDR and 70 dBFS SNR
(-1 BFS or 1.8 Vpp input) - 85 dBc SFDR (-6 dBFS or 1 Vpp input)
- 3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR and SFDR Trade-Off
- Parallel CMOS and Double Data Rate (DDR) LVDS Output Options
- Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Clock Amplitude Down to 400 mVPP
- Clock Duty Cycle Stabilizer
- Internal Reference with Support for External Reference
- External Decoupling Eliminated for References
- Programmable Output Clock Position and Drive Strength to Ease Data Capture
- 3.3 V Analog and 1.8 V to 3.3 V Digital Supply
- 32-pin QFN Package (5 mm × 5 mm)
- Pin Compatible 12-Bit Family (ADS612X)
- Temperature range -40°C to 85°C
- APPLICATIONS
- Wireless Communications Infrastructure
- Software Defined Radio
- Power Amplifier Linearization
- 802.16d/e
- Test and Measurement Instrumentation
- High Definition Video
- Medical Imaging
- Radar Systems
ADS61B23 is a 12-bit A/D converter (ADC) with a maximum sampling frequency of 80 MSPS. It combines high performance and low power consumption in a compact 32-QFN package. The analog inputs use buffers to isolate the switching transients of the internal sample & hold from the external driving circuit. The buffered inputs present very low input capacitance (< 2pF) & wide bandwidth. This makes it easy to drive them at high input frequencies, compared to an ADC without the input buffers.
ADS61B23 has coarse and fine gain options that are used to improve SFDR performance at lower full-scale analog input ranges.
The digital data outputs are parallel CMOS or DDR LVDS (Double Data Rate). Several features exist to ease data capture—controls for output clock position and output buffer drive strength, plus LVDS current and internal termination programmability.
The output interface type, gain, and other functions are programmed using a 3-wire serial interface. Alternatively, some of these functions are configured using dedicated parallel pins so the device starts in the desired state after power-up.
ADS61B23 includes internal references, while eliminating the traditional reference pins and associated external decoupling. External reference mode is also supported.
Technical documentation
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View all 9 | Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | 12Bits 80MSPS ADC with Buffered Analog Inputs datasheet | 07 Feb 2008 | |
| Application note | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 22 May 2015 | ||
| Application note | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 19 Jul 2013 | ||
| Application note | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 10 Sep 2010 | ||
| Application note | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 28 Apr 2009 | ||
| Application note | CDCE62005 as Clock Solution for High-Speed ADCs | 04 Sep 2008 | ||
| Application note | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 08 Jun 2008 | ||
| Application note | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 02 Jun 2008 | ||
| Application note | QFN Layout Guidelines | 28 Jul 2006 |
Design & development
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| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| VQFN (RHB) | 32 | Ultra Librarian |
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