Product details

Number of input channels 16 Active supply current (Typ) (mA) 274 Supply voltage (Max) (V) 3.6 Operating temperature range (C) -40 to 85 Interface type JESD204B, LVDS Features Analog Front End (AFE)
Number of input channels 16 Active supply current (Typ) (mA) 274 Supply voltage (Max) (V) 3.6 Operating temperature range (C) -40 to 85 Interface type JESD204B, LVDS Features Analog Front End (AFE)
NFBGA (ZBV) 289 225 mm² 15 x 15
  • 16-Channel, Complete Analog Front-End (AFE):
    • LNA, VCAT, PGA, LPF, ADC, and CW Mixer
  • LNA with Programmable Gain:
    • Gain: 24 dB, 18 dB, and 12 dB
    • Linear Input Range:
      0.25 VPP, 0.5 VPP, and 1 VPP
    • Input-Referred Noise:
      0.63 nV/√Hz, 0.7 nV/√Hz, and 0.9 nV/√Hz
    • Programmable Active Termination
  • Voltage-Controlled Attenuator (VCAT): 40 dB
  • Programmable Gain Amplifier (PGA):
    24 dB and 30 dB
  • Total Signal Chain Gain: 54 dB (max)
  • 3rd-Order, Linear-Phase LPF:
    • 10 MHz, 15 MHz, 20 MHz, 30 MHz, 35 MHz,
      and 50 MHz
  • Analog-to-Digital Converter (ADC):
    • 14-Bit ADC: 75-dBFS SNR at 65 MSPS
    • 12-Bit ADC: 72-dBFS SNR at 80 MSPS
  • LVDS Interface Maximum Speed of 1 Gbps
  • Noise and Power Optimizations (Full-Channel):
    • 140 mW/Ch at 0.75 nV/√Hz, 65 MSPS
    • 91.5 mW/Ch at 1.1 nV/√Hz, 40 MSPS
    • 80 mW/Ch at CW Mode
  • Excellent Device-to-Device Gain Matching:
    • ±0.5 dB (typical) and ±1.1 dB (max)
  • Low Harmonic Distortion
  • Fast and Consistent Overload Recovery
  • Passive Mixer for CWD:
    • Low Close-In Phase Noise:
      –156 dBc/Hz at 1 kHz Off 2.5-MHz Carrier
    • Phase Resolution: λ / 16
    • Supports 16X, 8X, 4X, and 1X CW Clocks
    • CWD High-Pass Filter Rejects Undesired Low-
      Frequency Signals < 1 kHz
  • Digital Features:
    • Digital I/Q Demodulator after ADC:
      • Fractional Decimation Filter M = 1 to
        63 with 0.25X Increment Step
      • Data Throughput Reduction After
        Decimation
      • On-Chip RAM with 32 Preset Profiles
  • 5-Gbps JESD Interface:
    • JESD204B Subclass 0, 1, and 2
    • 2, 4, or 8 Channels per JESD Lane
  • Small Package: 15-mm × 15-mm NFBGA-289
  • 16-Channel, Complete Analog Front-End (AFE):
    • LNA, VCAT, PGA, LPF, ADC, and CW Mixer
  • LNA with Programmable Gain:
    • Gain: 24 dB, 18 dB, and 12 dB
    • Linear Input Range:
      0.25 VPP, 0.5 VPP, and 1 VPP
    • Input-Referred Noise:
      0.63 nV/√Hz, 0.7 nV/√Hz, and 0.9 nV/√Hz
    • Programmable Active Termination
  • Voltage-Controlled Attenuator (VCAT): 40 dB
  • Programmable Gain Amplifier (PGA):
    24 dB and 30 dB
  • Total Signal Chain Gain: 54 dB (max)
  • 3rd-Order, Linear-Phase LPF:
    • 10 MHz, 15 MHz, 20 MHz, 30 MHz, 35 MHz,
      and 50 MHz
  • Analog-to-Digital Converter (ADC):
    • 14-Bit ADC: 75-dBFS SNR at 65 MSPS
    • 12-Bit ADC: 72-dBFS SNR at 80 MSPS
  • LVDS Interface Maximum Speed of 1 Gbps
  • Noise and Power Optimizations (Full-Channel):
    • 140 mW/Ch at 0.75 nV/√Hz, 65 MSPS
    • 91.5 mW/Ch at 1.1 nV/√Hz, 40 MSPS
    • 80 mW/Ch at CW Mode
  • Excellent Device-to-Device Gain Matching:
    • ±0.5 dB (typical) and ±1.1 dB (max)
  • Low Harmonic Distortion
  • Fast and Consistent Overload Recovery
  • Passive Mixer for CWD:
    • Low Close-In Phase Noise:
      –156 dBc/Hz at 1 kHz Off 2.5-MHz Carrier
    • Phase Resolution: λ / 16
    • Supports 16X, 8X, 4X, and 1X CW Clocks
    • CWD High-Pass Filter Rejects Undesired Low-
      Frequency Signals < 1 kHz
  • Digital Features:
    • Digital I/Q Demodulator after ADC:
      • Fractional Decimation Filter M = 1 to
        63 with 0.25X Increment Step
      • Data Throughput Reduction After
        Decimation
      • On-Chip RAM with 32 Preset Profiles
  • 5-Gbps JESD Interface:
    • JESD204B Subclass 0, 1, and 2
    • 2, 4, or 8 Channels per JESD Lane
  • Small Package: 15-mm × 15-mm NFBGA-289

The AFE58JD18 is a highly-integrated, analog front-end (AFE) solutions specifically designed for ultrasound systems where high performance and small size are required.

To request a full datasheet or other design resources: request AFE58JD18

The AFE58JD18 has a total of 16 channels, with each channel consisting of a voltage-controlled amplifier (VCA), a simultaneous sampling 14-bit and 12-bit analog-to-digital converter (ADC), and a continuous wave (CW) mixer. The VCA includes a low-noise amplifier (LNA), a voltage-controlled attenuator (VCAT), a programmable gain amplifier (PGA), and a low-pass filter (LPF). LNA gain is programmable and supports 250-mVPP to 1-VPP input signals and programmable active termination. The ultra-low noise VCAT provides an attenuation control range of 40 dB and improves overall low-gain SNR, which benefits harmonic and near-field imaging. The PGA provides gain options of 24 dB and 30 dB. In front of the ADC, an LPF can be configured at 10 MHz, 15 MHz, 20 MHz, 30 MHz, 35 MHz, or 50 MHz to support ultrasound applications with different frequencies.

The AFE58JD18 also integrates a low-power passive mixer and a low-noise summing amplifier to create an on-chip CWD beamformer. 16 selectable phase delays can be applied to each analog input signal. Furthermore, a unique third- and fifth-order harmonic suppression filter is implemented to enhance CW sensitivity

The high-performance, 14-bit ADC achieves 75-dBFS SNR. This ADC ensures excellent SNR at low-chain gain. The device can operate at maximum speeds of 65 MSPS and 80 MSPS, providing a 14-bit and a 12-bit output, respectively.

The ADC low-voltage differential signaling (LVDS) outputs enable a flexible system integration that is desirable for miniaturized systems.

The AFE58JD18 additionally includes an optional digital demodulator and JESD204B data packing blocks after the 12- or 14-bit ADC. The digital in-phase and quadrature (I/Q) demodulator with programmable fractional decimation filters accelerates computationally-intensive algorithms at low power. A JESD204B interface that runs up to 5 Gbps further reduces the circuit board routing challenges in high-channel count systems.

The AFE58JD18 also allows various power and noise combinations to be selected to optimize system performance. Therefore, the AFE58JD18 is a suitable ultrasound AFE solution for both high-end and portable systems.

The AFE58JD18 is available in a 15-mm × 15-mm NFBGA-289 package (ZBV package, S-PBGA-N289) and is specified for operation from –40°C to 85°C. The device pinout is also similar to the AFE5816 device family.

The AFE58JD18 is a highly-integrated, analog front-end (AFE) solutions specifically designed for ultrasound systems where high performance and small size are required.

To request a full datasheet or other design resources: request AFE58JD18

The AFE58JD18 has a total of 16 channels, with each channel consisting of a voltage-controlled amplifier (VCA), a simultaneous sampling 14-bit and 12-bit analog-to-digital converter (ADC), and a continuous wave (CW) mixer. The VCA includes a low-noise amplifier (LNA), a voltage-controlled attenuator (VCAT), a programmable gain amplifier (PGA), and a low-pass filter (LPF). LNA gain is programmable and supports 250-mVPP to 1-VPP input signals and programmable active termination. The ultra-low noise VCAT provides an attenuation control range of 40 dB and improves overall low-gain SNR, which benefits harmonic and near-field imaging. The PGA provides gain options of 24 dB and 30 dB. In front of the ADC, an LPF can be configured at 10 MHz, 15 MHz, 20 MHz, 30 MHz, 35 MHz, or 50 MHz to support ultrasound applications with different frequencies.

The AFE58JD18 also integrates a low-power passive mixer and a low-noise summing amplifier to create an on-chip CWD beamformer. 16 selectable phase delays can be applied to each analog input signal. Furthermore, a unique third- and fifth-order harmonic suppression filter is implemented to enhance CW sensitivity

The high-performance, 14-bit ADC achieves 75-dBFS SNR. This ADC ensures excellent SNR at low-chain gain. The device can operate at maximum speeds of 65 MSPS and 80 MSPS, providing a 14-bit and a 12-bit output, respectively.

The ADC low-voltage differential signaling (LVDS) outputs enable a flexible system integration that is desirable for miniaturized systems.

The AFE58JD18 additionally includes an optional digital demodulator and JESD204B data packing blocks after the 12- or 14-bit ADC. The digital in-phase and quadrature (I/Q) demodulator with programmable fractional decimation filters accelerates computationally-intensive algorithms at low power. A JESD204B interface that runs up to 5 Gbps further reduces the circuit board routing challenges in high-channel count systems.

The AFE58JD18 also allows various power and noise combinations to be selected to optimize system performance. Therefore, the AFE58JD18 is a suitable ultrasound AFE solution for both high-end and portable systems.

The AFE58JD18 is available in a 15-mm × 15-mm NFBGA-289 package (ZBV package, S-PBGA-N289) and is specified for operation from –40°C to 85°C. The device pinout is also similar to the AFE5816 device family.

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Technical documentation

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Type Title Date
* Data sheet AFE58JD18 16-Channel, Ultrasound AFE with 14-Bit, 65-MSPS or 12-Bit, 80-MSPS ADC, Passive CW Mixer, I/Q Demodulator, and LVDS, JESD204B Outputs datasheet (Rev. A) 27 May 2016
Application note Understanding CW Mode for Ultrasound AFE Devices 17 Jul 2017
Application note Time Gain Control (Compensation) in Ultrasound Applications 02 Dec 2016
Technical article Offset correction improves the next generation of heart-rate smart watches 24 Aug 2015
Technical article JESD204B: Is it for you? 14 Mar 2014
Technical article A new way to illuminate the human condition 30 Dec 2013
Technical article Oximeter signaling: There’s more than meets the eye 04 Dec 2013

Design & development

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Evaluation board

AFE58JD18EVM — AFE58JD18 Evaluation Module

The AFE58JD18EVM is a highly integrated Analog Front-End (AFE) solution specifically designed for ultrasound systems in which high performance and small size are required. The AFE58JD18EVM integrates a complete time-gain-control (TGC) imaging path and a continuous wave Doppler (CWD) path. It also (...)

Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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