Product details

Number of input channels 32 Active supply current (Typ) (mA) 40 Supply voltage (Max) (V) 3.3 Operating temperature range (C) -40 to 85 Interface type JESD204B, LVDS Features Analog Front End (AFE)
Number of input channels 32 Active supply current (Typ) (mA) 40 Supply voltage (Max) (V) 3.3 Operating temperature range (C) -40 to 85 Interface type JESD204B, LVDS Features Analog Front End (AFE)
NFBGA (ZBV) 289 225 mm² 15 x 15
  • 32-Channel, AFE for Ultrasound Applications:
    • Input Attenuator, LNA, LPF, ADC,
      Digital I/Q Demodulator and CW Mixer
    • Digital Time Gain Compensation (DTGC)
    • Total Gain Range: 12 dB to 51 dB
    • Linear Input Range: 800 mVPP
  • Input Attenuator With DTGC:
    • 8-dB to 0-dB Attenuation With 0.125-dB Step
    • Supports Matched Impedance for:
      • 50-Ω to 800-Ω Source Impedance
  • Low-Noise Amplifier (LNA) With DTGC:
    • 20-dB to 51-dB Gain With 0.125-dB Step
    • Low Input Current Noise: 1.2 pA/√Hz
  • 3rd-Order, Linear-Phase, Low-Pass Filter (LPF):
    • 5 MHz, 7.5 MHz, 10 MHz, and 12.5 MHz
  • 16 ADCs Converting at 12-Bit, 80 MSPS or 10-bit, 100 MSPS:
    • Each ADC Converts Two Sets of Inputs at Half Rate
    • 12-Bit ADC: 72-dBFS SNR
    • 10-Bit ADC: 61-dBFS SNR
  • Optimized for Noise and Power:
    • 35 mW/Ch at 2.1 nV/√Hz, 40 MSPS
    • 42 mW/Ch at 1.4 nV/√Hz, 40 MSPS
    • 52 mW/Ch at 1.3 nV/√Hz, 40 MSPS
    • 60 mW/Ch in CW Mode
  • Excellent Device-to-Device Gain Matching:
    • ±0.5 dB (Typical)
  • Low Harmonic Distortion: –55 dBc
  • Fast and Consistent Overload Recovery
  • Continuous Wave (CW) Path With:
    • Low Close-In Phase Noise of –151 dBc/Hz
      at 1-kHz Frequency Offset Off 2.5-MHz Carrier
    • Phase Resolution: λ / 16
    • Supports 16X CW Clock
    • 12-dB Suppression on Third and Fifth Harmonics
  • Digital I/Q Demodulator After ADC:
    • Decimation Filter M = 1 to 63
    • Data Throughput Reduction After Decimation
    • On-Chip RAM with 32 Preset Profiles
  • LVDS Interface With a Speed Up to 1 Gbps
  • 5-Gbps JESD Interface:
    • JESD204B Subclass 0, 1, and 2
    • 2, 4, or 8 Channels per JESD Lane
  • Small Package: 15-mm × 15-mm NFBGA-289
  • 32-Channel, AFE for Ultrasound Applications:
    • Input Attenuator, LNA, LPF, ADC,
      Digital I/Q Demodulator and CW Mixer
    • Digital Time Gain Compensation (DTGC)
    • Total Gain Range: 12 dB to 51 dB
    • Linear Input Range: 800 mVPP
  • Input Attenuator With DTGC:
    • 8-dB to 0-dB Attenuation With 0.125-dB Step
    • Supports Matched Impedance for:
      • 50-Ω to 800-Ω Source Impedance
  • Low-Noise Amplifier (LNA) With DTGC:
    • 20-dB to 51-dB Gain With 0.125-dB Step
    • Low Input Current Noise: 1.2 pA/√Hz
  • 3rd-Order, Linear-Phase, Low-Pass Filter (LPF):
    • 5 MHz, 7.5 MHz, 10 MHz, and 12.5 MHz
  • 16 ADCs Converting at 12-Bit, 80 MSPS or 10-bit, 100 MSPS:
    • Each ADC Converts Two Sets of Inputs at Half Rate
    • 12-Bit ADC: 72-dBFS SNR
    • 10-Bit ADC: 61-dBFS SNR
  • Optimized for Noise and Power:
    • 35 mW/Ch at 2.1 nV/√Hz, 40 MSPS
    • 42 mW/Ch at 1.4 nV/√Hz, 40 MSPS
    • 52 mW/Ch at 1.3 nV/√Hz, 40 MSPS
    • 60 mW/Ch in CW Mode
  • Excellent Device-to-Device Gain Matching:
    • ±0.5 dB (Typical)
  • Low Harmonic Distortion: –55 dBc
  • Fast and Consistent Overload Recovery
  • Continuous Wave (CW) Path With:
    • Low Close-In Phase Noise of –151 dBc/Hz
      at 1-kHz Frequency Offset Off 2.5-MHz Carrier
    • Phase Resolution: λ / 16
    • Supports 16X CW Clock
    • 12-dB Suppression on Third and Fifth Harmonics
  • Digital I/Q Demodulator After ADC:
    • Decimation Filter M = 1 to 63
    • Data Throughput Reduction After Decimation
    • On-Chip RAM with 32 Preset Profiles
  • LVDS Interface With a Speed Up to 1 Gbps
  • 5-Gbps JESD Interface:
    • JESD204B Subclass 0, 1, and 2
    • 2, 4, or 8 Channels per JESD Lane
  • Small Package: 15-mm × 15-mm NFBGA-289

The AFE58JD32 device is a highly-integrated, analog front-end solution specifically designed for ultrasound systems where high performance, low power, and small size are required.

The AFE58JD32 is an integrated analog front-end (AFE) optimized for medical ultrasound application. The device is realized through a multichip module (MCM) with three dies: two voltage-controlled amplifier (VCA) dies and one analog-to-digital converter (ADC) die. Each VCA die has 16 channels and the ADC die converts all of the 32 channels.

Each channel in the VCA die is configured in either of two modes: time gain compensation (TGC) mode or continuous wave (CW) mode. In TGC mode, each channel includes an input attenuator (ATTEN), a low-noise amplifier (LNA) with variable-gain, and a third-order, low-pass filter (LPF). The attenuator supports an attenuation range of 8 dB to 0 dB, and the LNA supports gain ranges from 20 dB to 51 dB. The LPF cutoff frequency can be configured at 5 MHz, 7.5 MHz, 10 MHz, or 12.5 MHz to support ultrasound applications with different frequencies. In CW mode, each channel includes an LNA with a fixed gain of 18 dB, and a low-power passive mixer with 16 selectable phase delays. Different phase delays can be applied to each analog input signal to perform an on-chip beamforming operation. A harmonic filter in the CW mixer suppresses the third and fifth harmonic to enhance the sensitivity of the CW Doppler measurement.

The ADC die has 16 physical ADCs. Each ADC converts two sets of outputs – one from each VCA die. The ADC is configured to operate with a resolution of 12 bits or 10 bits. The ADC resolution can be traded off with conversion rate, and operates at maximum speeds of 80 MSPS and 100 MSPS at 12-bit and 10-bit resolution, respectively. The ADC is designed to scale its power with sampling rate. The output interface of the ADC comes out through a low-voltage differential signaling (LVDS) which can easily interface with low-cost field-programmable gate arrays (FPGAs).

The AFE58JD32 includes an optional digital demodulator and JESD204B data packing blocks. The digital in-phase and quadrature (I/Q) demodulator with programmable decimation filters accelerates computationally-intensive algorithms at low power. The device also supports an optional JESD204B interface that runs up to 5-Gbps and further reduces the circuit-board routing challenges in high-channel count systems.

The AFE58JD32 also allows various power and noise combinations to be selected for optimizing system performance. Therefore, this device is a suitable ultrasound AFE solution for systems with strict battery-life requirements.

The AFE58JD32 device is a highly-integrated, analog front-end solution specifically designed for ultrasound systems where high performance, low power, and small size are required.

The AFE58JD32 is an integrated analog front-end (AFE) optimized for medical ultrasound application. The device is realized through a multichip module (MCM) with three dies: two voltage-controlled amplifier (VCA) dies and one analog-to-digital converter (ADC) die. Each VCA die has 16 channels and the ADC die converts all of the 32 channels.

Each channel in the VCA die is configured in either of two modes: time gain compensation (TGC) mode or continuous wave (CW) mode. In TGC mode, each channel includes an input attenuator (ATTEN), a low-noise amplifier (LNA) with variable-gain, and a third-order, low-pass filter (LPF). The attenuator supports an attenuation range of 8 dB to 0 dB, and the LNA supports gain ranges from 20 dB to 51 dB. The LPF cutoff frequency can be configured at 5 MHz, 7.5 MHz, 10 MHz, or 12.5 MHz to support ultrasound applications with different frequencies. In CW mode, each channel includes an LNA with a fixed gain of 18 dB, and a low-power passive mixer with 16 selectable phase delays. Different phase delays can be applied to each analog input signal to perform an on-chip beamforming operation. A harmonic filter in the CW mixer suppresses the third and fifth harmonic to enhance the sensitivity of the CW Doppler measurement.

The ADC die has 16 physical ADCs. Each ADC converts two sets of outputs – one from each VCA die. The ADC is configured to operate with a resolution of 12 bits or 10 bits. The ADC resolution can be traded off with conversion rate, and operates at maximum speeds of 80 MSPS and 100 MSPS at 12-bit and 10-bit resolution, respectively. The ADC is designed to scale its power with sampling rate. The output interface of the ADC comes out through a low-voltage differential signaling (LVDS) which can easily interface with low-cost field-programmable gate arrays (FPGAs).

The AFE58JD32 includes an optional digital demodulator and JESD204B data packing blocks. The digital in-phase and quadrature (I/Q) demodulator with programmable decimation filters accelerates computationally-intensive algorithms at low power. The device also supports an optional JESD204B interface that runs up to 5-Gbps and further reduces the circuit-board routing challenges in high-channel count systems.

The AFE58JD32 also allows various power and noise combinations to be selected for optimizing system performance. Therefore, this device is a suitable ultrasound AFE solution for systems with strict battery-life requirements.

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* Data sheet AFE58JD32 32-Channel Ultrasound AFE With 35-mW/Channel Power, 2.1 nV/√Hz Noise, 12-Bit, 40-MSPS or 10-Bit, 50-MSPS Output, Passive CW Mixer, LVDS and JESD204B Interface, and Digital Demodulator datasheet (Rev. A) PDF | HTML 19 Apr 2018
Technical article Offset correction improves the next generation of heart-rate smart watches 24 Aug 2015
Technical article JESD204B: Is it for you? 14 Mar 2014
Technical article A new way to illuminate the human condition 30 Dec 2013
Technical article Oximeter signaling: There’s more than meets the eye 04 Dec 2013

Design & development

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Evaluation board

AFE58JD32EVM — AFE58JD32 32-channel ultrasound AFE with digital demodulator evaluation module

The AFE58JD32 is a highly-integrated, analog front-end (AFE) solution specifically designed for ultrasound systems where high performance and small size are required. The device integrates a complete time-gain-control (TGC) imaging path and a continuous-wave Doppler (CWD) path. The 32-channel (...)

Simulation model

AFE58JD32 IBIS Model (Rev. A) AFE58JD32 IBIS Model (Rev. A)

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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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SBAA278 Design Files SBAA278 Design Files

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NFBGA (ZBV) 289 View options

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