20-V, 16:1 single-ended, 1-channel analog multiplexer
Product details
Parameters
Package | Pins | Size
Features
- Low ON resistance: 125
(typ.) over 15 Vp-p signal-input range for VDD - VSS = 15 V
- High OFF resistance: channel leakage of ±10 pA (typ.) @ VDD - VSS = 10 V
- Matched switch characteristics: RON = 5
(typ.) for VDD - VSS = 15 V
- Very low quiescent power dissipation under all digital-control input and supply conditions: 0.2 uW (typ.) @ VDD - VSS = 10 V
- Binary address decoding on chip
- 5-V, 10-V, and 15-V parametric ratings
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100nA at 18 V and 25°C
- Meets all requirements of JEDEC Tentative Standard No. 13A, "Standard Specifications for Description of 'B' Series CMOS Devices"
- Applications:
- Analog and digital multiplexing and demultiplexing
- A/D and D/A conversion
- Siganl gating
* When these devices are used as demultiplexers, the channel in/out terminals are the outputs and the common out/in terminals are the inputs.
Description
CD4067B and CD4097B CMOS analog multiplexers/demultiplexers* are digitally controlled analog switches having low ON impedance, low OFF leakage current, and internal address decoding. In addition, the ON resistance is relatively constant over the full input-signal range. The CD4067B is a 16-channel multiplexer with four binary control inputs, A, B, C, D, and an inhibit input, arranged so that any combination of the inputs selects one switch.
The CD4097B is a differential 8-channel multiplexer having three binary control inputs, A, B, C, and an inhibit input. The inputs permit selection of one of eight pairs of switches.
A logic "1" present at the inhibit input turns all channels off.
The CD4067B and CD4097B types are supplied in 24-lead hermetic dual-in-line ceramic packages (F3A suffix), 24-lead dual-in-line plastic packages (E suffix), 24-lead small-outline packages (M, M96, and NSR suffixes), and 24-lead thin shrink small-outline packages (P and PWR suffixes).
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | CD4067B, CD4097B TYPES datasheet (Rev. B) | Jun. 16, 2003 |
Application note | Selecting the Right Texas Instruments Signal Switch (Rev. B) | Apr. 02, 2020 | |
Application note | Multiplexers and Signal Switches Glossary | Mar. 06, 2020 | |
Selection guide | Logic Guide (Rev. AB) | Jun. 12, 2017 | |
Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | Dec. 02, 2015 | |
User guide | LOGIC Pocket Data Book (Rev. B) | Jan. 16, 2007 | |
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | Jul. 08, 2004 | |
User guide | Signal Switch Data Book (Rev. A) | Nov. 14, 2003 | |
More literature | Logic Cross-Reference (Rev. A) | Oct. 07, 2003 | |
Application note | Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics | Dec. 03, 2001 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages. The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.
Features
- Quick testing of TI's leaded surface mount packages
- Allows leaded suface mount packages to be plugged into 100mil spaced bread board
- Supports TI's 8 most popular leaded packages with a single panel
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
SOIC (DW) | 24 | View options |
TSSOP (PW) | 24 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
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Support & training
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