Product details
Parameters
Package | Pins | Size
Features
- Medium-Speed Operation - tPLH, tPHL = 60 ns (typ.) at VDD = 10 V
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 18 V over full package-temperature range: 100 nA at 18 V and 25°C
- Noise margin (full package-temperature range) =
- 1 V at VDD = 5 V
- 2 V at VDD = 10 V
- 2.5 V at VDD = 15 V
- Standardized, symmetrical output characteristics
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
CD4073B Triple 3-Input AND Gate
CD4081B Quad 2-Input AND Gate
CD4082B Dual 4-Input AND Gate
Data sheet acquired from Harris Semiconductor
Description
CD4073B, CD4081B and CD4082B AND gates, provide the system designer with direct implementation of the AND function and supplement the existing family of CMOS gates.
The CD4073B, CD4081B, and CD4082B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).
Technical documentation
= Top documentation for this product selected by TI
| Type | Title | Date | |
|---|---|---|---|
| * | Datasheet | CD4073B, CD4081B, CD4082B TYPES datasheet (Rev. C) | Aug. 21, 2003 |
| Technical articles | How to keep your motor running safely | Jun. 04, 2020 | |
| Selection guide | Logic Guide (Rev. AB) | Jun. 12, 2017 | |
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | Dec. 02, 2015 | |
| User guide | LOGIC Pocket Data Book (Rev. B) | Jan. 16, 2007 | |
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | Jul. 08, 2004 | |
| User guide | Signal Switch Data Book (Rev. A) | Nov. 14, 2003 | |
| More literature | Logic Cross-Reference (Rev. A) | Oct. 07, 2003 | |
| Application note | Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics | Dec. 03, 2001 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
14-24-LOGIC-EVM
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
- Board design allows for versatility in evaluation
- Supports a wide-range of logic devices
Design tools & simulation
SCHM010.ZIP (7 KB) - PSpice Model
SCHM010A.ZIP (7 KB) - PSpice Model
Reference designs
TIDA-01051 — The TIDA-01051 reference design is used to demonstrate optimized channel density, integration, power consumption, clock distribution and signal chain performance of very high channel count data acquisition (DAQ) systems such as those used in automatic test equipment (ATE). Using serializers, such as (...)
Design files
-
download TIDA-01051 BOM.pdf (107KB) -
download TIDA-01051 Assembly Drawing.pdf (2002KB) -
download TIDA-01051 PCB.pdf (8638KB) -
download TIDA-01051 CAD Files.zip (15688KB) -
download TIDA-01051 Gerber.zip (1735KB)
CAD/CAE symbols
| Package | Pins | Download |
|---|---|---|
| PDIP (N) | 14 | View options |
| SO (NS) | 14 | View options |
| SOIC (D) | 14 | View options |
| TSSOP (PW) | 14 | View options |
Ordering & quality
Information included:
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Support & training
TI E2E™ forums with technical support from TI engineers
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