Reference Design Optimizing FPGA Utilization and Data Throughput for Automatic Test Equipment


Design files


The TIDA-01051 reference design is used to demonstrate optimized channel density, integration, power consumption, clock distribution and signal chain performance of very high channel count data acquisition (DAQ) systems such as those used in automatic test equipment (ATE). Using serializers, such as TI’s DS90C383B, to combine many simultaneously sampling ADC outputs into several LVDS lines dramatically reduces the number of pins the host FPGA must process.  As a result, a single FPGA can process a significantly increased number of DAQ channels and board routing complexity is greatly reduced.

  • Two 20 bit SAR ADC channels (expendable up to 28)
  • Three level MUX tree (up to 64 channels per ADC)
  • Highlights throughput improvements using serialized ADC output data
  • Modular front-end reference design for high channel count systems that can be repeated
  • Up to +/-12V input signal (+/-24Vpp differential)

A fully assembled board has been developed for testing and performance validation only, and is not available for sale.

Design files & products

Design files

Download ready-to-use system files to speed your design process.

TIDUCH2.PDF (6791 K)

Reference design overview and verified performance test data

TIDRQI8.PDF (2807 K)

Detailed schematic diagram for design layout and components


Complete listing of design components, reference designators, and manufacturers/part numbers

TIDRQJ0.PDF (2002 K)

Detailed overview of design layout for component placement

TIDRQJ2.ZIP (15688 K)

Files used for 3D models or 2D drawings of IC components

TIDCDB8.ZIP (1735 K)

Design file that contains information on physical board layer of design PCB

TIDRQJ1.PDF (8638 K)

PCB layer plot file used for generating PCB design layout


Includes TI products in the design and potential alternatives.

AND gates

CD4081B4-ch, 2-input, 3-V to 18-V AND gates

Data sheet: PDF
Analog switches & muxes

MUX36D041-pA on-state leakage current, 36-V, 4:1, 2-channel precision analog multiplexer

Data sheet: PDF | HTML
Buck converters (integrated switch)

LM460013.5 to 60V, 1A Synchronous Step-Down Voltage Converter

Data sheet: PDF | HTML
Buck converters (integrated switch)

LM53635-Q13.5-A, 36-V synchronous, 2.1-MHz, automotive step-down DC-DC converter

Data sheet: PDF | HTML
Buck modules (integrated inductor)

TPS820842-A, High-efficiency step-down converter module with integrated inductor

Data sheet: PDF | HTML
Charge pumps (inductorless)

LM7705Low Noise Negative Bias Generator

Data sheet: PDF | HTML
Clock buffers

LMK00804BLow skew, 1-to-4 multiplexed differential/LVCMOS-to-LVCMOS/TTL fanout buffer

Data sheet: PDF | HTML
D-type flip-flops

SN74AUP1G80Low-Power Single Postitive-Edge-Triggered D-Type Flip-Flop

Data sheet: PDF | HTML
FPD-Link SerDes

DS90C383B+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz

Data sheet: PDF
Fully differential amplifiers

THS4551Low Noise, Precision, 150MHz, Fully Differential Amplifier

Data sheet: PDF | HTML
High-speed op amps (GBW ≥ 50 MHz)

OPA625High Bandwidth, High Precision, Low Noise & Distortion Amplifier SAR ADC Driver with Power Scaling

Data sheet: PDF | HTML
Inverting buffers & drivers

SN74AHC1G04Single 2-V to 5.5-V inverter

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS7A3001-EPEnhanced product, negative VIN, 200-mA, ultra-low noise, high PSRR, LDO regular

Data sheet: PDF
Linear & low-dropout (LDO) regulators

TPS7A471-A, 36-V, low-noise, high-PSRR, low-dropout voltage regulator with enable

Data sheet: PDF | HTML

LMK61E2156.250-MHz, ±50 ppm, ultra-low jitter, integrated EEPROM, fully programmable oscillator

Data sheet: PDF | HTML
Precision ADCs

ADS8910B18-Bit, 1-MSPS, 1-Ch SAR ADC with Internal VREF Buffer, Internal LDO and Enhanced SPI Interface

Data sheet: PDF | HTML
Precision op amps (Vos<1mV)

OPA376Precision (0.025mV), low noise (7.5nV/rtHz), low quiescent current (760uA) op amp

Data sheet: PDF | HTML
Precision op amps (Vos<1mV)

OPA827Low-noise, high-precision, JFET-input operational amplifier

Data sheet: PDF | HTML
Series voltage references

REF60414.096-V, 5-ppm/°C high-precision voltage reference with integrated buffer & enable pin

Data sheet: PDF | HTML

Technical documentation

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Type Title Date
* Design guide Ref Design Optimizing FPGA and Data Throughput for High Channel Auto Testers Apr. 10, 2017

Related design resources

Reference designs

TIDA-00732 18-bit, 2-Msps Isolated Data Acquisition Reference Design to Achieve Maximum SNR and Sampling Rate TIDA-01035 20-bit Isolated Data Acquisition Reference Design Optimizing Jitter for Max SNR and Sample Rate TIDA-01037 20-bit, 1-MSPS Isolator Optimized Data Acquisition Reference Design Maximizing SNR and Sample Rate TIDA-01050 Optimized Analog Front End DAQ System Reference Design for 18 bit SAR Data Converters TIDA-01052 ADC Driver Reference Design Improving Full Scale THD Using Negative Supply TIDA-01053 ADC Driver Reference Design Optimizing THD, Noise, and SNR for High Dynamic Range Instrumentation TIDA-01054 Multi-Rail Power Reference Design for Eliminating EMI Effects in High Performance DAQ Systems TIDA-01055 ADC Voltage Reference Buffer Optimization Reference Design for High Performance DAQ Systems TIDA-01056 20-bit 1MSPS DAQ Reference Design Optimizing Power Supply Efficiency While Minimizing EMI TIDA-01057 Reference Design Maximizing Signal Dynamic Range for True 10 Vpp Differential Input to 20 bit ADC

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