CD74AC10

ACTIVE

Triple 3-Input NAND Gates

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Product details

Parameters

Technology Family AC VCC (Min) (V) 1.5 VCC (Max) (V) 5.5 Channels (#) 3 Inputs per channel 3 IOL (Max) (mA) 24 IOH (Max) (mA) -24 Input type Standard CMOS Output type Push-Pull Features Over-Voltage Tolerant Inputs, Standard Speed (tpd > 50ns) Data rate (Max) (Mbps) 100 Rating Catalog Operating temperature range (C) -55 to 125 open-in-new Find other NAND gate

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 open-in-new Find other NAND gate

Features

  • AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage
  • Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
  • Balanced Propagation Delays
  • ±24-mA Output Drive Current
    • Fanout to 15 F Devices
  • SCR Latchup-Resistant CMOS Process and Circuit Design
  • Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015

open-in-new Find other NAND gate

Description

The CD74AC10 contains three independent 3-input NAND gates. This device performs the Boolean function Y = (A •B • C)\ or Y = A\ + B\ + C\ in positive logic.

open-in-new Find other NAND gate
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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet CD74AC10 datasheet Nov. 04, 2002
Technical articles How to keep your motor running safely Jun. 04, 2020
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
More literature HiRel Unitrode Power Management Brochure Jul. 07, 2009
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODELS Download
SCHM038.ZIP (7 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SOIC (D) 14 View options

Ordering & quality

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