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Logic & voltage translation
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Noninverting buffers & drivers

CD74HC4050

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6-ch, 2-V to 6-V buffers

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Data sheet

CD74HC4050

ACTIVE
Data sheet Order now

Product details

Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Number of channels 6 IOL (max) (mA) 4 Supply current (max) (µA) 40 IOH (max) (mA) -4 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, High speed (tpd 10-50ns), Input clamp diode Rating Catalog Operating temperature range (°C) -55 to 125
Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Number of channels 6 IOL (max) (mA) 4 Supply current (max) (µA) 40 IOH (max) (mA) -4 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, High speed (tpd 10-50ns), Input clamp diode Rating Catalog Operating temperature range (°C) -55 to 125
PDIP (N) 16 181.42 mm² 19.3 x 9.4 SOIC (D) 16 59.4 mm² 9.9 x 6 SOP (NS) 16 79.56 mm² 10.2 x 7.8 TSSOP (PW) 16 32 mm² 5 x 6.4
  • Typical Propagation Delay: 6ns at VCC = 5V, CL = 15pF, TA = 25°C
  • High-to-Low Voltage Level Converter for up to VI = 16V
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • Typical Propagation Delay: 6ns at VCC = 5V, CL = 15pF, TA = 25°C
  • High-to-Low Voltage Level Converter for up to VI = 16V
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V

The ’HC4049 and ’HC4050 are fabricated with high-speed silicon gate technology. They have a modified input protection structure that enables these parts to be used as logic level translators which convert high-level logic to a low-level logic while operating off the low-level logic supply. For example, 15-V input pulse levels can be down-converted to 0-V to 5-V logic levels. The modified input protection structure protects the input from negative electrostatic discharge. These parts also can be used as simple buffers or inverters without level translation. The ’HC4049 and ’HC4050 are enhanced versions of equivalent CMOS types.

The ’HC4049 and ’HC4050 are fabricated with high-speed silicon gate technology. They have a modified input protection structure that enables these parts to be used as logic level translators which convert high-level logic to a low-level logic while operating off the low-level logic supply. For example, 15-V input pulse levels can be down-converted to 0-V to 5-V logic levels. The modified input protection structure protects the input from negative electrostatic discharge. These parts also can be used as simple buffers or inverters without level translation. The ’HC4049 and ’HC4050 are enhanced versions of equivalent CMOS types.
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Technical documentation

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Type Title Date
* Data sheet CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050 datasheet (Rev. I) 04 Feb 2005
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 May 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

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Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

User guide: PDF | HTML
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Simulation model

CD74HC4050 Behavioral SPICE Model

SCHM086.ZIP (7 KB) - PSpice Model
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Package Pins Download
PDIP (N) 16 View options
SOIC (D) 16 View options
SOP (NS) 16 View options
TSSOP (PW) 16 View options
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