Product details

Technology Family HCT Supply voltage (Min) (V) 4.5 Supply voltage (Max) (V) 5.5 Number of channels (#) 6 IOL (Max) (mA) 5.2 IOH (Max) (mA) -5.2 ICC (Max) (uA) 40 Input type TTL-Compatible CMOS Output type Push-Pull Features Balanced outputs, High speed (tpd 10-50ns), Input clamp diode Rating Catalog
Technology Family HCT Supply voltage (Min) (V) 4.5 Supply voltage (Max) (V) 5.5 Number of channels (#) 6 IOL (Max) (mA) 5.2 IOH (Max) (mA) -5.2 ICC (Max) (uA) 40 Input type TTL-Compatible CMOS Output type Push-Pull Features Balanced outputs, High speed (tpd 10-50ns), Input clamp diode Rating Catalog
PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 TSSOP (PW) 14 32 mm² 5 x 6.4
  • LSTTL input logic compatible
    • VIL(max) = 0.8 V, VIH(min) = 2 V
  • CMOS input logic compatible
    • II ≤ 1 µA at VOL, VOH
  • Buffered inputs
  • 4.5 V to 5.5 V operation
  • Wide operating temperature range: -55°C to +125°C
  • Supports fanout up to 10 LSTTL loads
  • Significant power reduction compared to LSTTL logic ICs
  • LSTTL input logic compatible
    • VIL(max) = 0.8 V, VIH(min) = 2 V
  • CMOS input logic compatible
    • II ≤ 1 µA at VOL, VOH
  • Buffered inputs
  • 4.5 V to 5.5 V operation
  • Wide operating temperature range: -55°C to +125°C
  • Supports fanout up to 10 LSTTL loads
  • Significant power reduction compared to LSTTL logic ICs

This device contains six independent inverters. Each gate performs the Boolean function Y =  A in positive logic.

This device contains six independent inverters. Each gate performs the Boolean function Y =  A in positive logic.

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Technical documentation

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Type Title Date
* Data sheet CD54HCT04, CD74HCT04 High-Speed CMOS Logic Hex Inverter datasheet 29 Aug 2019
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 May 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

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Simulation model

CD74HCT04 Behavioral SPICE Model

SCHM095.ZIP (7 KB) - PSpice Model
Package Pins Download
PDIP (N) 14 View options
SOIC (D) 14 View options
TSSOP (PW) 14 View options

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