CD74HCT125 High Speed CMOS Logic Quad Buffers with 3-State Outputs | TI.com

CD74HCT125
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High Speed CMOS Logic Quad Buffers with 3-State Outputs

High Speed CMOS Logic Quad Buffers with 3-State Outputs - CD74HCT125
Datasheet
 

Description

The ’HC125 and ’HCT125 contain 4 independent three-state buffers, each having its own output enable input, which when "HIGH" puts the output in the high impedance state.

Features

  • Three-State Outputs
  • Separate Output Enable Inputs
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . -55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH

Data sheet acquired from Harris Semiconductor

Parametrics

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Part number Order Technology Family VCC (Min) (V) VCC (Max) (V) Channels (#) IOL (Max) (mA) IOH (Max) (mA) ICC (uA) Input type Output type Features Data rate (Mbps) Rating Package Group
CD74HCT125 Order now HCT     4.5     5.5     4     6     -6     160     TTL-Compatible CMOS     3-State     Balanced outputs
High speed (tpd 10-50ns)
Input clamp diode    
50     Catalog     PDIP | 14
SOIC | 14    
CD54HCT125 Samples not available HCT     4.5     5.5     4     6     -6     80     Standard CMOS     Push-Pull     Standard speed (tpd > 50ns)     50     Military     CDIP | 14