CD74HCT4066-Q1

ACTIVE

Product details

Configuration 1:1 SPST Number of channels 4 Power supply voltage - single (V) 5 Protocols Analog Ron (typ) (Ω) 25 CON (typ) (pF) 5 ON-state leakage current (max) (µA) 1 Bandwidth (MHz) 200 Operating temperature range (°C) -40 to 125 Input/output continuous current (max) (mA) 25 Rating Automotive Drain supply voltage (max) (V) 5.5 Supply voltage (max) (V) 5.5
Configuration 1:1 SPST Number of channels 4 Power supply voltage - single (V) 5 Protocols Analog Ron (typ) (Ω) 25 CON (typ) (pF) 5 ON-state leakage current (max) (µA) 1 Bandwidth (MHz) 200 Operating temperature range (°C) -40 to 125 Input/output continuous current (max) (mA) 25 Rating Automotive Drain supply voltage (max) (V) 5.5 Supply voltage (max) (V) 5.5
SOIC (D) 14 51.9 mm² 8.65 x 6 TSSOP (PW) 14 32 mm² 5 x 6.4
  • Qualified for Automotive Applications
  • Low ON Resistance
    • 25 Ω Typical (VCC = 4.5 V)
  • Fast Switching and Propagation Speeds
  • Low OFF Leakage Current
  • Wide Operating Temperature Range: –40°C to 125°C
  • Direct LSTTL Input Logic Compatibility:
        VIL = 0.8 V Max, VIH = 2 V Min
  • CMOS Input Compatibility: II ≤ 1 µA at VOL, VOH

  • Qualified for Automotive Applications
  • Low ON Resistance
    • 25 Ω Typical (VCC = 4.5 V)
  • Fast Switching and Propagation Speeds
  • Low OFF Leakage Current
  • Wide Operating Temperature Range: –40°C to 125°C
  • Direct LSTTL Input Logic Compatibility:
        VIL = 0.8 V Max, VIH = 2 V Min
  • CMOS Input Compatibility: II ≤ 1 µA at VOL, VOH

The CD74HCT4066 contains four independent digitally controlled analog switches that use silicon-gate CMOS technology to achieve operation speeds similar to LSTTL, with the low power consumption of standard CMOS integrated circuits.

These switches feature the characteristic linear ON resistance of the metal-gate CD4066B. Each switch is turned on by a high-level voltage on its control input.

The CD74HCT4066 contains four independent digitally controlled analog switches that use silicon-gate CMOS technology to achieve operation speeds similar to LSTTL, with the low power consumption of standard CMOS integrated circuits.

These switches feature the characteristic linear ON resistance of the metal-gate CD4066B. Each switch is turned on by a high-level voltage on its control input.

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Technical documentation

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Type Title Date
* Data sheet Highe-Speed CMOS Logic Quad Bilateral Switch datasheet (Rev. B) 24 Apr 2008
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 30 Apr 2024
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 02 Jun 2022
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 01 Dec 2021
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
More literature Automotive Logic Devices Brochure 27 Aug 2014
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 May 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

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Interface adapter

LEADED-ADAPTER1 — Surface mount to DIP header adapter for quick testing of TI's 5, 8, 10, 16 & 24-pin leaded packages

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

User guide: PDF
Not available on TI.com
Package Pins CAD symbols, footprints & 3D models
SOIC (D) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian

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