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CDCDB803

ACTIVE

8-output clock buffer for PCIe® Gen 1 to Gen 6 with selectable SMBus addresses

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Data sheet

CDCDB803

ACTIVE
Data sheet Order now

Product details

Number of outputs 8 Additive RMS jitter (typ) (fs) 38 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Output skew (ps) 50 Operating temperature range (°C) -40 to 105 Rating Catalog Output type LP-HCSL Input type LP-HCSL
Number of outputs 8 Additive RMS jitter (typ) (fs) 38 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Output skew (ps) 50 Operating temperature range (°C) -40 to 105 Rating Catalog Output type LP-HCSL Input type LP-HCSL
VQFN (RSL) 48 36 mm² 6 x 6
  • 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations
  • 8 hardware output enable (OE#) controls
  • Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum)
  • Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (maximum)
  • Additive phase jitter after DB2000Q filter: 38 fs, RMS (maximum)
  • Supports Common Clock (CC) and Individual Reference (IR) architectures
    • Spread spectrum-compatible
  • Output-to-output skew: < 50 ps
  • Input-to-output delay: < 3 ns

  • Fail-safe input

  • Programmable output slew rate control

  • 9 selectable SMBus addresses
  • 3.3-V core and IO supply voltages
  • Hardware-controlled low power mode (PD#)
  • Current consumption: 72 mA maximum
  • 6-mm × 6-mm, 48-pin VQFN package
  • 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations
  • 8 hardware output enable (OE#) controls
  • Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum)
  • Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (maximum)
  • Additive phase jitter after DB2000Q filter: 38 fs, RMS (maximum)
  • Supports Common Clock (CC) and Individual Reference (IR) architectures
    • Spread spectrum-compatible
  • Output-to-output skew: < 50 ps
  • Input-to-output delay: < 3 ns

  • Fail-safe input

  • Programmable output slew rate control

  • 9 selectable SMBus addresses
  • 3.3-V core and IO supply voltages
  • Hardware-controlled low power mode (PD#)
  • Current consumption: 72 mA maximum
  • 6-mm × 6-mm, 48-pin VQFN package

The CDCDB803 is a 8-output LP-HCSL, DB800ZL-compliant, clock buffer capable of distributing the reference clock for PCIe Gen 1-6, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces. The SMBus interface and eight output enable pins allow the configuration and control of all eight outputs individually. The CDCDB803 is a DB800ZL derivative buffer and meets or exceeds the system parameters in the DB800ZL specification. It also meets or exceeds the parameters in the DB2000Q specification. The CDCDB803 is packaged in a 6-mm × 6-mm, 48-pin VQFN package.

The CDCDB803 is a 8-output LP-HCSL, DB800ZL-compliant, clock buffer capable of distributing the reference clock for PCIe Gen 1-6, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces. The SMBus interface and eight output enable pins allow the configuration and control of all eight outputs individually. The CDCDB803 is a DB800ZL derivative buffer and meets or exceeds the system parameters in the DB800ZL specification. It also meets or exceeds the parameters in the DB2000Q specification. The CDCDB803 is packaged in a 6-mm × 6-mm, 48-pin VQFN package.
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* Data sheet CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6 datasheet (Rev. A) PDF | HTML 23 May 2022

Design & development

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Evaluation board

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