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CDCE18005

ACTIVE

5/10 outputs clock buffer with divider

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Data sheet

CDCE18005

ACTIVE
Data sheet Order now

Product details

Number of outputs 5 Additive RMS jitter (typ) (fs) 200 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Output skew (ps) 25 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVPECL Input type LVPECL
Number of outputs 5 Additive RMS jitter (typ) (fs) 200 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Output skew (ps) 25 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVPECL Input type LVPECL
VQFN (RGZ) 48 49 mm² 7 x 7
  • Universal Input Buffers That Accept LVPECL, LVDS, or LVCMOS Level Signaling
  • Fully Configurable Outputs Including Frequency, Output Format, and Output Skew
  • Output Multiplexer That Serves as a Clock Switch Between the Three Reference Inputs
    and the Outputs
  • Clock Generation Via AT-Cut Crystal
  • Integrated EEPROM Determines Device Configuration at Power-up
  • Low Additive Jitter Performance
  • Universal Output Blocks Support up to 5 Differential, 10 Single-ended, or
    Combinations of Differential or Single-ended:
    • Low Additive Jitter
    • Output Frequency up to 1.5 GHz
    • LVPECL, LVDS, LVCMOS, and Special High Output Swing Modes
    • Independent Output Dividers Support Divide Ratios from 1–80
    • Independent limited Coarse Skew Control on all Outputs
  • Flexible Inputs:
    • Two Universal Differential Inputs Accept Frequencies up to 1500 MHz (LVPECL),
      800 MHz (LVDS), or 250 MHz (LVCMOS).
    • One Auxiliary Input Accepts Crystal. Auxiliary Input Accepts Crystals in the Range of
      2 MHz–42 MHz
    • Clock Generator Mode Using Crystal Input.
  • Typical Power Consumption 1W at 3.3V
  • Offered in QFN-48 Package
  • ESD Protection Exceeds 2kV HBM
  • Industrial Temperature Range –40°C to 85°C
  • Universal Input Buffers That Accept LVPECL, LVDS, or LVCMOS Level Signaling
  • Fully Configurable Outputs Including Frequency, Output Format, and Output Skew
  • Output Multiplexer That Serves as a Clock Switch Between the Three Reference Inputs
    and the Outputs
  • Clock Generation Via AT-Cut Crystal
  • Integrated EEPROM Determines Device Configuration at Power-up
  • Low Additive Jitter Performance
  • Universal Output Blocks Support up to 5 Differential, 10 Single-ended, or
    Combinations of Differential or Single-ended:
    • Low Additive Jitter
    • Output Frequency up to 1.5 GHz
    • LVPECL, LVDS, LVCMOS, and Special High Output Swing Modes
    • Independent Output Dividers Support Divide Ratios from 1–80
    • Independent limited Coarse Skew Control on all Outputs
  • Flexible Inputs:
    • Two Universal Differential Inputs Accept Frequencies up to 1500 MHz (LVPECL),
      800 MHz (LVDS), or 250 MHz (LVCMOS).
    • One Auxiliary Input Accepts Crystal. Auxiliary Input Accepts Crystals in the Range of
      2 MHz–42 MHz
    • Clock Generator Mode Using Crystal Input.
  • Typical Power Consumption 1W at 3.3V
  • Offered in QFN-48 Package
  • ESD Protection Exceeds 2kV HBM
  • Industrial Temperature Range –40°C to 85°C

The CDCE18005 is a high performance clock distributor featuring a high degree of configurability via a SPI interface, and programmable start up modes determined by on-chip EEPROM. Specifically tailored for buffering clocks for data converters and high-speed digital signals, the CDCE18005 achieves low additive jitter in the 50 fs RMS(1) range. The clock distribution block includes five individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique output frequency (up to 1.5 GHz(2)

The CDCE18005 is a high performance clock distributor featuring a high degree of configurability via a SPI interface, and programmable start up modes determined by on-chip EEPROM. Specifically tailored for buffering clocks for data converters and high-speed digital signals, the CDCE18005 achieves low additive jitter in the 50 fs RMS(1) range. The clock distribution block includes five individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique output frequency (up to 1.5 GHz(2)
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Type Title Date
* Data sheet Five/Ten Output Clock Programmable Buffer datasheet (Rev. B) 21 Nov 2012
User guide Low Phase Noise Clock Evaluation Module — up to 1.5 Ghz 11 Nov 2008

Design & development

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Evaluation board

CDCE18005EVM — CDCE18005EVM Evaluation Module

The CDCE18005 is a high performance clock generator and distributor featuring a high degree of configurability via a SPI interface, and programmable start up modes determined by on-board EEPROM. Specifically tailored for buffering clocks for data converters and high-speed digital signals, the (...)
User guide: PDF
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Support software

SCAC106 — CDCE18005 EVM Control Software installer

Supported products & hardware

Supported products & hardware

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Clock buffers
  • CDCE18005 — 5/10 outputs clock buffer with divider
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CDCE18005 IBIS Model

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PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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VQFN (RGZ) 48 Ultra Librarian
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