Product details

Function Clock generator Number of outputs 1 Output frequency (Max) (MHz) 1100 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVCMOS Output type LVDS Operating temperature range (C) -40 to 85 Features Design tool available, Integrated EEPROM, Serial interface Rating Catalog
Function Clock generator Number of outputs 1 Output frequency (Max) (MHz) 1100 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVCMOS Output type LVDS Operating temperature range (C) -40 to 85 Features Design tool available, Integrated EEPROM, Serial interface Rating Catalog
VQFN (RGE) 24 16 mm² 4 x 4
  • Single Supply at 3.3 V for LVPECL or LVDS Operation
  • High-Performance Clock Multiplier, Incorporating Crystal Oscillator Circuitry with Integrated Frequency Synthesizer
  • Low Output Jitter: 380 fs RMS typical (from 10 kHz to 20 MHz)
  • Low Phase Noise at High Frequency (708-MHz LVPECL):
    • Typically -109 dBc/Hz at 10 kHz and -146dBc/Hz at 10 MHz from the carrier
  • Supports Crystal or LVCMOS Input Frequencies from 27.35 MHz to 38.33 MHz
  • Output Frequency Ranges from 10.9 MHz to 766.7 MHz and from 875.2 MHz to 1175 MHz
  • Low-Voltage Differential Signaling (LVDS) Output, 100- Differential Off-Chip Termination, 10.9-MHz to 400-MHz Frequency Range
  • Differential Low-Voltage Positive Emitter Coupled Logic (LVPECL) Outputs, 10.9-MHz to 1.175-GHz Frequency Range
  • Two Fully-Integrated Voltage-Controlled Oscillators (VCO) Support Wide Output Frequency Range
  • Fully Integrated Programmable Loop Filter
  • Typical Power Consumption at 3.3 V:
    • 274 mW in LVDS mode
    • 250 mW in LVPECL mode
  • Chip Enable Control Pin
  • Simple Serial Interface Allows Programming after Manufacturing
  • Integrated On-Chip Nonvolatile Memory (EEPROM) Stores Settings Without Applying High Voltage
  • Available in 4-mm × 4-mm QFN-24 Package
  • ESD Protection Exceeds 2 kV (HBM)
  • Industrial Temperature Range: -40°C to +85°C
  • APPLICATIONS
    • Low-Cost, High-Frequency Crystal Oscillator

All trademarks are the property of their respective owners.

  • Single Supply at 3.3 V for LVPECL or LVDS Operation
  • High-Performance Clock Multiplier, Incorporating Crystal Oscillator Circuitry with Integrated Frequency Synthesizer
  • Low Output Jitter: 380 fs RMS typical (from 10 kHz to 20 MHz)
  • Low Phase Noise at High Frequency (708-MHz LVPECL):
    • Typically -109 dBc/Hz at 10 kHz and -146dBc/Hz at 10 MHz from the carrier
  • Supports Crystal or LVCMOS Input Frequencies from 27.35 MHz to 38.33 MHz
  • Output Frequency Ranges from 10.9 MHz to 766.7 MHz and from 875.2 MHz to 1175 MHz
  • Low-Voltage Differential Signaling (LVDS) Output, 100- Differential Off-Chip Termination, 10.9-MHz to 400-MHz Frequency Range
  • Differential Low-Voltage Positive Emitter Coupled Logic (LVPECL) Outputs, 10.9-MHz to 1.175-GHz Frequency Range
  • Two Fully-Integrated Voltage-Controlled Oscillators (VCO) Support Wide Output Frequency Range
  • Fully Integrated Programmable Loop Filter
  • Typical Power Consumption at 3.3 V:
    • 274 mW in LVDS mode
    • 250 mW in LVPECL mode
  • Chip Enable Control Pin
  • Simple Serial Interface Allows Programming after Manufacturing
  • Integrated On-Chip Nonvolatile Memory (EEPROM) Stores Settings Without Applying High Voltage
  • Available in 4-mm × 4-mm QFN-24 Package
  • ESD Protection Exceeds 2 kV (HBM)
  • Industrial Temperature Range: -40°C to +85°C
  • APPLICATIONS
    • Low-Cost, High-Frequency Crystal Oscillator

All trademarks are the property of their respective owners.

The CDCE421A is a high-performance, low phase noise clock generator. It has two fully-integrated, low-noise, LC-based voltage-controlled oscillators (VCOs) that operate in the 1.750-GHz to 2.350-GHz frequency range. It also features an integrated crystal oscillator that operates in conjunction with an external AT-cut crystal to produce a stable frequency reference for the phase-locked loop (PLL) based frequency synthesizer.

The output frequency (fOUT) is proportional to the frequency of the input crystal (fXTAL). The prescaler divider, feedback divider, output divider, and VCO selection set the output frequency with respect to fXTAL.

In the CDCE421A, the feedback divider is set automatically with respect to the prescaler setting. The product of the prescaler and the feedback divider should be between 60 and 64 as shown in to maintain a stable control loop.

The CDCE421A supports one differential LVDS clock output or one differential LVPECL output. All device settings are programmable through a proprietary simple serial interface (SSI).

The device operates in 3.3-V supply environment for both LVPECL and LVDS outputs and is characterized for operation from -40°C to +85°C. The CDCE421A is available in a QFN-24 4-mm × 4-mm package.

CDCE421 Users:

The CDCE421A provides several device enhancements to the CDCE421.

The CDCE421A is a high-performance, low phase noise clock generator. It has two fully-integrated, low-noise, LC-based voltage-controlled oscillators (VCOs) that operate in the 1.750-GHz to 2.350-GHz frequency range. It also features an integrated crystal oscillator that operates in conjunction with an external AT-cut crystal to produce a stable frequency reference for the phase-locked loop (PLL) based frequency synthesizer.

The output frequency (fOUT) is proportional to the frequency of the input crystal (fXTAL). The prescaler divider, feedback divider, output divider, and VCO selection set the output frequency with respect to fXTAL.

In the CDCE421A, the feedback divider is set automatically with respect to the prescaler setting. The product of the prescaler and the feedback divider should be between 60 and 64 as shown in to maintain a stable control loop.

The CDCE421A supports one differential LVDS clock output or one differential LVPECL output. All device settings are programmable through a proprietary simple serial interface (SSI).

The device operates in 3.3-V supply environment for both LVPECL and LVDS outputs and is characterized for operation from -40°C to +85°C. The CDCE421A is available in a QFN-24 4-mm × 4-mm package.

CDCE421 Users:

The CDCE421A provides several device enhancements to the CDCE421.

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Technical documentation

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Type Title Date
* Data sheet CDCE421A datasheet 21 Apr 2009
Technical article How to select an optimal clocking solution for your FPGA-based design 09 Dec 2015
Technical article Clocking sampled systems to minimize jitter 31 Jul 2014
Technical article Timing is Everything: How to optimize clock distribution in PCIe applications 28 Mar 2014
User guide CDCE421AEVM User Guide 02 Jun 2009

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

GUI for evaluation module (EVM)

CDCE421A Control GUI v1.0

SCAC111.ZIP (363 KB)
Simulation tool

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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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