CDCEL824

ACTIVE

Programmable 2-PLL clock synthesizer with spread spectrum capability

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Product details

Parameters

Function Clock generator Number of outputs 4 Output frequency (Max) (MHz) 201 Core supply voltage (V) 1.8 Output supply voltage (V) 1.8 Input type XTAL, LVCMOS Output type LVCMOS Operating temperature range (C) -40 to 85 Features Integrated EEPROM, Spread-spectrum clocking (SSC) Rating Catalog open-in-new Find other Clock generators

Package | Pins | Size

TSSOP (PW) 16 22 mm² 5 x 4.4 open-in-new Find other Clock generators

Features

  • Flexible Clock Driver
    • Three User-Definable Control Inputs
      [S0/S1/S2]: for example, Frequency Switching,
      Output Enable, or Power Down
    • Enables 0-PPM Clock Generation
  • In-System Programmability and EEPROM
    • Serial Programmable Volatile Register
    • Nonvolatile EEPROM to Store Customer
      Settings
  • Flexible Input Clocking Concept
    • External Crystal: 20 MHz to 30 MHz
    • Single-Ended LVCMOS up to 130 MHz
  • Selectable Output Frequency up to 201 MHz
  • Low-Noise PLL Core
    • PLL Loop Filter Components Integrated
    • Low Period Jitter (Typical 80 ps)
  • 1.8-V Device Power Supply
  • Temperature Range –40°C to 85°C
  • Packaged in TSSOP
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Description

The CDCEL824 is a modular PLL-based low-cost, high-performance, programmable clock synthesizer, multiplier, and divider. It generates up to four output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 201 MHz, using up to two independent configurable PLLs.

The CDCEL824 has a separate output supply pins, VDDOUT, which are 1.8 V.

The input accepts an external crystal or LVCMOS clock signal. In case of a crystal input, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 pF to 20 pF.

The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, Bluetooth, Ethernet, GPS) or interface (USB, IEEE1394, memory stick) clocks from a 27-MHz reference input frequency, for example.

Based on the PLL frequency and the divider settings, the internal loop filter components are automatically adjusted to achieve high stability and optimized jitter transfer characteristic of each PLL.

The device supports nonvolatile EEPROM programming for easy customization of the device in the application. It is preset to a factory default configuration and can be reprogrammed to a different application configuration before it goes onto the PCB or reprogrammed by in-system programming. All device settings are programmable through the SDA/SCL bus, a 2-wire serial interface.

Three free programmable control inputs, S0, S1, and S2, can be used to select different frequencies, or other control features like outputs disable to low, outputs in high-impedance state, power down, PLL bypass, and so forth.

The CDCx824 operates in a 1.8-V environment in a temperature range of –40°C to 85°C.

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Technical documentation

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Type Title Date
* Data sheet CDCEL824 Programmable 2-PLL Clock Synthesizer datasheet (Rev. A) Sep. 09, 2015
Technical article How to select an optimal clocking solution for your FPGA-based design Dec. 09, 2015
Technical article Clocking sampled systems to minimize jitter Jul. 31, 2014
Technical article Timing is Everything: How to optimize clock distribution in PCIe applications Mar. 28, 2014

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Clock tree architect programming software
CLOCK-TREE-ARCHITECT Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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  • Accepts customer specific design requirements such as input frequencies, output frequencies, clock formats and clock counts
  • Generates clock trees by taking into account a variety of advanced specifications, such as noise floor and phase determinism requirements
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TSSOP (PW) 16 View options

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