CY74FCT652T

ACTIVE

Octal Bus Transceivers and Registers with 3-State Outputs

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Product details

Parameters

Technology Family FCT VCC (Min) (V) 4.75 VCC (Max) (V) 5.25 Bits (#) 8 Voltage (Nom) (V) 5 F @ nom voltage (Max) (MHz) 70 ICC @ nom voltage (Max) (mA) 0.2 Propagation delay (Max) (ns) 9 IOL (Max) (mA) 64 IOH (Max) (mA) -32 Operating temperature range (C) -40 to 85 open-in-new Find other Registered transceiver

Package | Pins | Size

SOIC (DW) 24 160 mm² 15.5 x 10.3 SSOP (DBQ) 24 52 mm² 8.65 x 6 open-in-new Find other Registered transceiver

Features

  • Function, Pinout, and Drive Compatible With FCT and F Logic
  • Reduced VOH (Typically = 3.3 V) Version of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • 64-mA Output Sink Current
    32-mA Output Source Current
  • Independent Register for A and B Buses
  • Multiplexed Real-Time and Stored Data Transfer
  • 3-State Outputs

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Description

The CY74FCT652T consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal storage registers. GAB and GBA\ inputs control the transceiver functions. Select-control (SAB and SBA) inputs select either real-time or stored-data transfer. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A low input level selects real-time data, and a high input level selects stored data.

Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions of the appropriate clock (CPAB or CPBA) inputs, regardless of the select or enable levels of the control pins. When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the internal D-type flip-flops by simultaneously enabling GAB and GBA\. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Technical documentation

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Type Title Date
* Datasheet 8-Bit Registered Transceiver With 3-State Outputs datasheet (Rev. B) Oct. 24, 2001
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
User guides CYFCT Parameter Measurement Information Apr. 02, 2001
Selection guides Advanced Bus Interface Logic Selection Guide Jan. 09, 2001

Design & development

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Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
SOIC (DW) 24 View options
SSOP (DBQ) 24 View options

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