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High-speed DACs (>10MSPS)

DAC5672

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Dual-Channel, 14-Bit, 275-MSPS Digital-to-Analog Converter (DAC)

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Data sheet

DAC5672

ACTIVE
Data sheet Order now

Product details

Resolution (Bits) 14 Number of DAC channels (#) 2 Interface type Parallel CMOS Sample/update rate (MSPS) 275 Features Low Power Rating Catalog Interpolation 1x Power consumption (Typ) (mW) 330 SFDR (dB) 84 Architecture Current Source Operating temperature range (C) -40 to 85 Reference type Int
Resolution (Bits) 14 Number of DAC channels (#) 2 Interface type Parallel CMOS Sample/update rate (MSPS) 275 Features Low Power Rating Catalog Interpolation 1x Power consumption (Typ) (mW) 330 SFDR (dB) 84 Architecture Current Source Operating temperature range (C) -40 to 85 Reference type Int
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TQFP (PFB) 48 81 mm² 9 x 9
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  • 14-Bit Dual Transmit Digital-to-Analog Converter (DAC)
  • 275 MSPS Update Rate
  • Single-Supply: 3 V to 3.6 V
  • High Spurious-Free Dynamic Range (SFDR): 84 dBc at 5 MHz
  • High Third-Order Two-Tone Intermodulation (IMD3): 79 dBc at 15.1 MHz and 16.1 MHz
  • WCDMA Adjacent Channel Leakage Ratio (ACLR): 78 dB at Baseband
  • WCDMA ACLR: 73 dB at 30.72 MHz
  • Independent or Single Resistor Gain Control
  • Dual or Interleaved Data
  • On-Chip 1.2-V Reference
  • Low Power: 330 mW
  • Power-Down Mode: 9 mW
  • Package: 48-Pin Thin-Quad Flat Pack (TQFP)
  • 14-Bit Dual Transmit Digital-to-Analog Converter (DAC)
  • 275 MSPS Update Rate
  • Single-Supply: 3 V to 3.6 V
  • High Spurious-Free Dynamic Range (SFDR): 84 dBc at 5 MHz
  • High Third-Order Two-Tone Intermodulation (IMD3): 79 dBc at 15.1 MHz and 16.1 MHz
  • WCDMA Adjacent Channel Leakage Ratio (ACLR): 78 dB at Baseband
  • WCDMA ACLR: 73 dB at 30.72 MHz
  • Independent or Single Resistor Gain Control
  • Dual or Interleaved Data
  • On-Chip 1.2-V Reference
  • Low Power: 330 mW
  • Power-Down Mode: 9 mW
  • Package: 48-Pin Thin-Quad Flat Pack (TQFP)
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The DAC5672 device is a monolithic, dual-channel, 14-bit, high-speed DAC with on-chip voltage reference.

Operating with update rates of up to 275 MSPS, the DAC5672 offers exceptional dynamic performance, tight-gain, and offset matching characteristics that make the device well-suited in I/Q baseband or direct IF communication applications.

Each DAC has a high-impedance, differential-current output suitable for single-ended or differential analog-output configurations. External resistors allow scaling the full-scale output current for each DAC separately or together, typically between 2 mA and 20 mA. An accurate on-chip voltage reference is temperature-compensated and delivers a stable 1.2-V reference voltage. Optionally, an external reference may be used.

The DAC5672 has two, 14-bit, parallel input ports with separate clocks and data latches. For flexibility, the DAC5672 supports multiplexed data for each DAC on one port when operating in interleaved mode.

The DAC5672 is specifically designed for a differential transformer-coupled output with a 50-Ω doubly-terminated load. For a 20-mA full-scale output current, a 4:1 impedance ratio (resulting in an output power of 4 dBm) and 1:1 impedance ratio transformer (–2 dBm output power) are supported.

The DAC5672 is available in a 48-pin TQFP package. Pin compatibility between family members provides 12-bit (DAC5662) and 14-bit (DAC5672) resolutions. Furthermore, the DAC5672 is pin compatible to the DAC2904 and AD9767 dual DACs. The device is characterized for operation over the industrial temperature range from –40°C to 85°C.

The DAC5672 device is a monolithic, dual-channel, 14-bit, high-speed DAC with on-chip voltage reference.

Operating with update rates of up to 275 MSPS, the DAC5672 offers exceptional dynamic performance, tight-gain, and offset matching characteristics that make the device well-suited in I/Q baseband or direct IF communication applications.

Each DAC has a high-impedance, differential-current output suitable for single-ended or differential analog-output configurations. External resistors allow scaling the full-scale output current for each DAC separately or together, typically between 2 mA and 20 mA. An accurate on-chip voltage reference is temperature-compensated and delivers a stable 1.2-V reference voltage. Optionally, an external reference may be used.

The DAC5672 has two, 14-bit, parallel input ports with separate clocks and data latches. For flexibility, the DAC5672 supports multiplexed data for each DAC on one port when operating in interleaved mode.

The DAC5672 is specifically designed for a differential transformer-coupled output with a 50-Ω doubly-terminated load. For a 20-mA full-scale output current, a 4:1 impedance ratio (resulting in an output power of 4 dBm) and 1:1 impedance ratio transformer (–2 dBm output power) are supported.

The DAC5672 is available in a 48-pin TQFP package. Pin compatibility between family members provides 12-bit (DAC5662) and 14-bit (DAC5672) resolutions. Furthermore, the DAC5672 is pin compatible to the DAC2904 and AD9767 dual DACs. The device is characterized for operation over the industrial temperature range from –40°C to 85°C.

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Technical documentation

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Type Title Date
* Data sheet Dual 14 Bit 275 MSPS DAC datasheet (Rev. D) 04 Aug 2017
Technical article Keys to quick success using high-speed data converters 13 Oct 2020
Technical article Digital signal processing in RF sampling DACs – part 2 04 Apr 2017
Technical article Digital signal processing in RF sampling DACs - part 1 13 Feb 2017
Technical article Why phase noise matters in RF sampling converters 28 Nov 2016
User guide TSW6011EVM Quick Start Guide (Rev. D) 17 Aug 2016
Application note Wideband Complementary Current Output DAC Single-Ended Interface (Rev. A) 08 May 2015
Design guide Direct Down-Conversion System With I/Q Correction (TIDA-00078 CerTIfied Design) 23 Jul 2013
Application note High Speed, Digital-to-Analog Converters Basics (Rev. A) 23 Oct 2012
Application note Passive Terminations for Current Output DACs 10 Nov 2008
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 08 Jun 2008
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 02 Jun 2008
User guide DAC5672/62/52 14- and 12-Bit Dual Channel DAC EVM (Rev. B) 24 Mar 2006

Design & development

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Evaluation board

DAC5672EVM — DAC5672 Dual-Channel, 14-Bit, 275-MSPS Digital-to-Analog Converter Evaluation Module

This tool is designed to enable DAC5672 evaluation under various signals, reference and supply conditions.

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Simulation model

DAC5672 IBIS Model (Rev. A)

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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Calculation tool

MATCHGAIN-CALC — Wideband Comp Current Output DAC to SE Interface: Impr Matching for Gain & Compliance Volt Swing

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Reference designs

TIDA-00078 — Direct Down-Conversion System with I/Q Correction

The I/Q Correction block implemented in the Field Programmable Gate Array (FPGA) of the TSW6011EVM helps users to adopt a direct down conversion receiver architecture in a wireless system. The I/Q correction block consists of a single-tap blind algorithm, which corrects the frequency-independent (...)
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TQFP (PFB) 48 View options

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