DRV3245Q-Q1

• AEC-Q100 qualified for automotive applications:
  • Device temperature grade 1:
    –40°C to +125°C, T_A
• SafeTI™semiconductor component
  • Developed according to the applicable requirements of ISO 26262
• 4.5-V to 45-V operating voltage
• Programmable peak gate drive currents up to 1A
• Charge-pump gate driver for 100% Duty Cycle
• Current-shunt amplifiers and phase comparators
  • A / C Device: 3 current-shunt amplifiers⁽¹⁾ and 3-phase comparators with status through SPI ⁽¹⁾
  • B Device: 2 current-shunt amplifiers and 3-phase comparators with real-time monitor through digital pins
• 3-PWM or 6-PWM input control up to 20 kHz
• Single PWM-mode commutation capability
• Supports both 3.3-V and 5-V digital interface
• Serial peripheral interface (SPI)
• Thermally-enhanced 48-Pin HTQFP
• Protection features:
  • Internal regulators, battery voltage monitor
  • SPI CRC
  • Clock monitor
  • Analog built-in self test
  • Programmable dead-time control
  • MOSFET shoot-through prevention
  • MOSFET V_DS overcurrent monitors
  • Gate-source voltage real time monitor
  • Overtemperature warning and Shutdown

⁽¹⁾C device : Low-drift offset high-precision amplifiers

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The DRV3245Q-Q1 device is a FET gate driver IC for three-phase motor-drive applications designed according to the applicable requirements of ISO 26262 for functional safety applications. The device provides three half-bridge drivers each capable of driving a high-side and low-side N-channel MOSFET while also providing sophisticated protection and monitoring of the FETs. A charge-pump driver enables 100% duty cycle and supports low battery voltages during cold-crank operation. The integration of current-sense amplifiers, integrated phase comparators, and SPI-based configuration of the driver and its peripherals enable reduction of the bill of materials (BOM) and space on the printed circuit board (PCB) because of the elimination of most external and passive components.

The DRV3245Q-Q1 device also integrates diagnostics and protection for each internal block and provides support for common system diagnostic checks each of which can be instantiated and reported through SPI. This flexibility of the integrated features allows the device to integrate seamlessly into a variety of safety architectures.