The DS90C383 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CF384 receiver converts the LVDS data streams back into 28 bits of CMOS/TTL data. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughputs is 227 Mbytes/sec. The transmitter is offered with programmable edge data strobes for convenient interface with a variety of graphics controllers. The transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge transmitter will inter-operate with a Falling edge receiver (DS90CF384) without any translation logic. The DS90CF384 is also offered in 64 ball, 0.8mm fine pitch ball grid array(FBGA) package which provides a 44 % reduction in PCB footprint (available Q3, 1999).
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | DS90C383/F384 3.3VProg LVDS Trans 24Bit FPD, 65MHz,3.3VLVDS Rcvr 24Bit FPD 65MHz datasheet (Rev. A) | May 13, 2004 | |
| Application note | How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) | Jun 29, 2018 | ||
| Application note | AN-1032 An Introduction to FPD-Link (Rev. C) | Aug 8, 2017 | ||
| Application note | Receiver Skew Margin for Channel Link I and FPD Link I Devices | PDF | HTML | Jan 13, 2016 | |
| Application note | TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map | May 15, 2004 | ||
| Application note | AN-1056 STN Application Using FPD-Link | May 14, 2004 | ||
| Application note | AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines | May 14, 2004 |
For additional terms or required resources, click any title below to view the detail page where available.
The FPD-Link evaluation kit includes a transmitter (Tx) board, a receiver (Rx) board and interfacing cables. This kit shows the chipsets interfacing from test equipment or a graphics controller using low-voltage differential signaling (LVDS) to a receiver board.
The transmitter board accepts (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| TSSOP (DGG) | 56 | Ultra Librarian |
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