Product details

Rating Catalog
Rating Catalog
PDIP (P) 8 93 mm² 9.81 x 9.43 SOIC (D) 14 52 mm² 8.65 x 6
  • Operates from ±5-V to ±18-V Supplies
  • Less than 10-µs Acquisition Time
  • Logic Input Compatible With TTL, PMOS, CMOS
  • 0.5-mV Typical Hold Step at Ch = 0.01 µF
  • Low Input Offset
  • 0.002% Gain Accuracy
  • Low Output Noise in Hold Mode
  • Input Characteristics Do Not Change During Hold Mode
  • High Supply Rejection Ratio in Sample or Hold
  • Wide Bandwidth
  • Space Qualified, JM38510
  • Operates from ±5-V to ±18-V Supplies
  • Less than 10-µs Acquisition Time
  • Logic Input Compatible With TTL, PMOS, CMOS
  • 0.5-mV Typical Hold Step at Ch = 0.01 µF
  • Low Input Offset
  • 0.002% Gain Accuracy
  • Low Output Noise in Hold Mode
  • Input Characteristics Do Not Change During Hold Mode
  • High Supply Rejection Ratio in Sample or Hold
  • Wide Bandwidth
  • Space Qualified, JM38510

The LFx98x devices are monolithic sample-and-hold circuits that use BI-FET technology to obtain ultrahigh DC accuracy with fast acquisition of signal and low droop rate. Operating as a unity-gain follower, DC gain accuracy is 0.002% typical and acquisition time is as low as 6 µs to 0.01%. A bipolar input stage is used to achieve low offset voltage and wide bandwidth. Input offset adjust is accomplished with a single pin and does not degrade input offset drift. The wide bandwidth allows the LFx98x to be included inside the feedback loop of 1-MHz operational amplifiers without having stability problems. Input impedance of 1010 Ω allows high-source impedances to be used without degrading accuracy.

P-channel junction FETs are combined with bipolar devices in the output amplifier to give droop rates as low as 5 mV/min with a 1-µF hold capacitor. The JFETs have much lower noise than MOS devices used in previous designs and do not exhibit high temperature instabilities. The overall design ensures no feedthrough from input to output in the hold mode, even for input signals equal to the supply voltages.

Logic inputs on the LFx98x are fully differential with low input current, allowing for direct connection to TTL, PMOS, and CMOS. Differential threshold is
1.4 V. The LFx98x will operate from ±5-V to ±18-V supplies.

An A version is available with tightened electrical specifications.

The LFx98x devices are monolithic sample-and-hold circuits that use BI-FET technology to obtain ultrahigh DC accuracy with fast acquisition of signal and low droop rate. Operating as a unity-gain follower, DC gain accuracy is 0.002% typical and acquisition time is as low as 6 µs to 0.01%. A bipolar input stage is used to achieve low offset voltage and wide bandwidth. Input offset adjust is accomplished with a single pin and does not degrade input offset drift. The wide bandwidth allows the LFx98x to be included inside the feedback loop of 1-MHz operational amplifiers without having stability problems. Input impedance of 1010 Ω allows high-source impedances to be used without degrading accuracy.

P-channel junction FETs are combined with bipolar devices in the output amplifier to give droop rates as low as 5 mV/min with a 1-µF hold capacitor. The JFETs have much lower noise than MOS devices used in previous designs and do not exhibit high temperature instabilities. The overall design ensures no feedthrough from input to output in the hold mode, even for input signals equal to the supply voltages.

Logic inputs on the LFx98x are fully differential with low input current, allowing for direct connection to TTL, PMOS, and CMOS. Differential threshold is
1.4 V. The LFx98x will operate from ±5-V to ±18-V supplies.

An A version is available with tightened electrical specifications.

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Technical documentation

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Type Title Date
* Data sheet LFx98x Monolithic Sample-and-Hold Circuits datasheet (Rev. C) 05 Oct 2018
Application note AN-298 Isolation Techniques for Signal Conditioning (Rev. B) 06 May 2013
Application note AN-301 Signal Conditioning for Sophisticated Transducers (Rev. B) 06 May 2013
Application note Applications of the LM3524 Pulse Width Modulator (Rev. B) 23 Apr 2013
Application note Using ADC0808/809 8-Bit uP Compble ADCs w/8-Chan Analog Multiplexr (Rev. B) 22 Apr 2013
More literature Die D/S LF398 MDC Monolithic Sample And Hold Circuit 07 Sep 2012
Application note Data Acq Using ADC0816 & ADC0817 8-Bit ADC w/On-Chip 16 Chan Multiplexr 10 May 2004
Application note AN-294 Special Sample and Hold Techniques 10 May 2004
Application note Specifications and Architectures of Sample-and-Hold Amplifiers 03 May 2004
Application note Freq-to-Vltg Converter Uses Sample-and-Hold to Improve Response & Ripple 03 Oct 2002

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