42V, Secondary Side Post Regulator/Synchronous Buck Controller with Power-Up/Power-Down Tracking
Product details
Parameters
Package | Pins | Size
Features
- Power-up/Power-down Tracking
- Self-synchronization to Main Channel Output
- Leading Edge Pulse Width Modulation
- Valley Current Mode Control
- Standalone DC/DC Synchronous Buck Mode
- Operates from AC or DC Input up to 42V
- Wide 4.5V to 30V Bias Supply Range
- Wide 0.75V to 13.5V Output Range.
- Top and Bottom Gate Drivers Sink 2.5A Peak
- Adaptive Gate Driver Dead-time Control
- Wide Bandwidth Error Amplifier (4MHz)
- Programmable Soft-start
- Thermal Shutdown Protection
- TSSOP-16 package
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Description
The LM25115A controller contains all of the features necessary to produce multiple tracking outputs using the Secondary Side Post Regulation (SSPR) technique. The SSPR technique develops a highly efficient and well regulated auxiliary output from the secondary side switching waveform of an isolated power converter. LM25115A can be also used as a standalone DC/DC synchronous buck controller (Refer to section). Regulation of the auxiliary output voltage is achieved by leading edge pulse width modulation (PWM) of the main channel duty cycle. Leading edge modulation is compatible with either current mode or voltage mode control of the main output. The LM25115A drives external high-side and low-side NMOS power switches configured as a synchronous buck regulator. A current sense amplifier provides overload protection and operates over a wide common mode input range. Additional features include a low dropout (LDO) bias regulator, error amplifier, precision reference, adaptive dead time control of the gate signals and thermal shutdown.
Technical documentation
| Type | Title | Date | |
|---|---|---|---|
| * | Datasheet | Secondary Side Post Regulator/DC-DC Converter with Power-Up/Pwr-Down Trac datasheet (Rev. B) | Apr. 01, 2013 |
| Selection guide | Power Management Guide 2018 (Rev. R) | Jun. 25, 2018 | |
| Application note | Reduce buck-converter EMI and voltage stress by minimizing inductive parasitics | Jul. 21, 2016 | |
| User guide | AN-1368 LM5115/5025A Evaluation Board (Rev. A) | Apr. 26, 2013 | |
| User guide | AN-1367 LM5115 HV DC Evaluation Board (Rev. B) | Apr. 24, 2013 | |
| User guide | AN-1542 LM5115A Evaluation Board (Rev. B) | Apr. 24, 2013 | |
| Application note | Minimizing FET Losses For a High Input Rail Buck Converter (Rev. A) | Apr. 23, 2013 |
Design & development
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Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
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CAD/CAE symbols
| Package | Pins | Download |
|---|---|---|
| TSSOP (PW) | 16 | View options |
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