LMK00804B-Q1

ACTIVE

Automotive, 1.5-V to 3.3-V, 1-to-4 high-performance LVCMOS fanout buffer & level translator

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Automotive, 1.5-V to 3.3-V, 1-to-4 high-performance LVCMOS fanout buffer & level translator

LMK00804B-Q1

ACTIVE

Product details

Parameters

Function Single-ended Additive RMS jitter (Typ) (fs) 40 Output frequency (Max) (MHz) 350 Number of outputs 4 Output supply voltage (V) 1.5, 1.8, 2.5, 3.3 Core supply voltage (V) 3.3 Output skew (ps) 35 Features Glitch-free output clock Operating temperature range (C) -40 to 125 Rating Automotive Output type LVCMOS Input type HCSL, LVCMOS, LVDS, LVPECL, LVTTL open-in-new Find other Clock buffers

Package | Pins | Size

VQFN (RGT) 16 9 mm² 3 x 3 open-in-new Find other Clock buffers

Features

  • AEC-Q100 qualified with the following results:
    • Device temperature grade 1: –40°C to +125°C, TA
  • Four LVCMOS/LVTTL outputs supporting 1.5-V to 3.3-V levels
    • Additive jitter: 0.1-ps RMS (typical) at 40 MHz
    • Noise floor: –168 dBc/Hz (typical) at 40 MHz
    • Output frequency: 350 MHz (maximum)
    • Output skew: 35 ps (maximum)
    • Part-to-part skew: 550 ps (maximum)
  • Two selectable inputs
    • CLK_P, CLK_N pair accepts LVPECL, LVDS, HCSL, SSTL, LVHSTL, or LVCMOS/LVTTL
    • LVCMOS_CLK accepts LVCMOS/LVTTL
  • Synchronous clock enable
  • Core/output power supplies:
    • 3.3 V/3.3 V
    • 3.3 V/2.5 V
    • 3.3 V/1.8 V
    • 3.3 V/1.5 V
  • Package: 16-pin VQFN

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Description

The LMK00804B-Q1 is a high-performance clock fan-out buffer and level translator that can distribute up to four LVCMOS/LVTTL outputs (3.3-V, 2.5-V, 1.8-V, or 1.5-V levels) from one of two selectable inputs that can accept differential or single-ended inputs. The clock enable input is synchronized internally to eliminate runt or glitch pulses on the outputs when the clock enable terminal is asserted or deasserted. The outputs are held in logic low state when the clock is disabled. The LMK00804B-Q1 can also distribute a low-jitter clock across four transceivers and can improve the overall target detection and resolution in a cascaded mmWave radar system.

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Technical documentation

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Type Title Date
* Data sheet LMK00804B-Q1 1.5-V to 3.3-V, 1-to-4 High-Performance LVCMOS Fan-Out Buffer and Level Translator datasheet (Rev. B) Aug. 26, 2019
User guide LMK00804B-Q1EVM User’s guide (Rev. A) Aug. 26, 2019

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
299
Description
The LMK00804B-Q1 is a low skew, high performance clock fan-out buffer, which distributes up to four LVCMOS/LVTTL outputs (3.3-V, 2.5-V, 1.8-V, or 1.5-V levels).  The clocks are derived from one of two selectable inputs, which can accept differential or single-ended input signals. The (...)
Features
  • Easy to use evaluation board to fan-out up to four LVCMOS clocks with low phase noise/jitter
  • Accepts differential or single-ended/LVCMOS input clock
  • Device control pins configurable through jumpers
  • Board power at 3.3-V for VDD and VDDO (single supply), or 2.5-V/1.8-V/1.5-V for VDDO (dual supply)

Design tools & simulation

SIMULATION MODEL Download
SNAM230.ZIP (55 KB) - IBIS Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
DESIGN TOOL Download
Clock tree architect programming software
CLOCK-TREE-ARCHITECT Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
Features
  • Accepts customer specific design requirements such as input frequencies, output frequencies, clock formats and clock counts
  • Generates clock trees by taking into account a variety of advanced specifications, such as noise floor and phase determinism requirements
  • Presents clear and intuitive block (...)

Reference designs

REFERENCE DESIGNS Download
Imaging radar using cascaded mmWave sensor reference design
TIDEP-01012 The cascade development kit has two main use cases:
  1. To use the MMWCAS-DSP-EVM as a capture card to fully evaluate the AWR2243 four-chip cascade performance by using the mmWave studio tool, please read the TIDEP-01012 design guide.
  2. To use the MMWCAS-DSP-EVM to develop radar real time SW application (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
VQFN (RGT) 16 View options

Ordering & quality

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  • Qualification summary
  • Ongoing reliability monitoring

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