SN74ABT240A

ACTIVE

Octal Buffers/Drivers With 3-State Outputs

Top

Product details

Parameters

Technology Family ABT VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Channels (#) 8 IOL (Max) (mA) 64 IOH (Max) (mA) -32 ICC (Max) (uA) 5.5 Input type TTL-Compatible CMOS Output type 3-State Features Ultra high speed (tpd <5ns), Partial power down (Ioff), Over-voltage tolerant inputs Data rate (Mbps) 300 Rating Catalog open-in-new Find other Inverting buffer/driver

Package | Pins | Size

PDIP (N) 20 229 mm² 24.33 x 9.4 SOIC (DW) 20 132 mm² 12.8 x 10.3 SOP (NS) 20 98 mm² 12.6 x 7.8 SSOP (DB) 20 38 mm² 5.3 x 7.2 TSSOP (PW) 20 42 mm² 6.5 x 6.4 open-in-new Find other Inverting buffer/driver

Features

  • Typical VOLP (Output Ground Bounce)
       <1 V at VCC = 5 V, TA = 25°C
  • High-Drive Outputs (–32-mA IOH, 64-mA IOL)
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

open-in-new Find other Inverting buffer/driver

Description

These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Together with the SN54ABT241, SN74ABT241A, SN54ABT244, and SN74ABT244A, these devices provide the choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable (OE)\ inputs, and complementary OE and OE\ inputs.

The SN54ABT240 and SN74ABT240A are organized as two 4-bit buffers/line drivers with separate OE\ inputs. When OE\ is low, the devices pass inverted data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

open-in-new Find other Inverting buffer/driver
Download

Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 20
Type Title Date
* Datasheet Octal Buffers/Drivers With 3-State Outputs datasheet (Rev. I) Jun. 13, 2002
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
Application notes Quad Flatpack No-Lead Logic Packages (Rev. D) Feb. 16, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices May 10, 2002
Selection guides Advanced Bus Interface Logic Selection Guide Jan. 09, 2001
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A) Mar. 01, 1997
Application notes Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A) Dec. 01, 1996
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes Understanding Advanced Bus-Interface Products Design Guide May 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODELS Download
SCBM143.ZIP (7 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
PDIP (N) 20 View options
SO (NS) 20 View options
SOIC (DW) 20 View options
SSOP (DB) 20 View options
TSSOP (PW) 20 View options

Ordering & quality

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos

Related videos