These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Together with the SN54ABT241, SN74ABT241A, SN54ABT244, and SN74ABT244A, these devices provide the choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable (OE)\ inputs, and complementary OE and OE\ inputs.
The SN54ABT240 and SN74ABT240A are organized as two 4-bit buffers/line drivers with separate OE\ inputs. When OE\ is low, the devices pass inverted data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
|Part number||Order||Technology Family||VCC (Min) (V)||VCC (Max) (V)||Channels (#)||IOL (Max) (mA)||IOH (Max) (mA)||ICC (uA)||Input type||Output type||Features||Data rate (Mbps)||Rating||Operating temperature range (C)||Package Group|
Ultra high speed (tpd <5ns)
Partial power down (Ioff)
Over-voltage tolerant inputs
|300||Catalog||-40 to 85||
PDIP | 20
SOIC | 20
SO | 20
SSOP | 20
TSSOP | 20