Product details

Technology Family AHCT Supply voltage (Min) (V) 4.5 Supply voltage (Max) (V) 5.5 Number of channels (#) 8 IOL (Max) (mA) 8 IOH (Max) (mA) -8 ICC (Max) (uA) 40 Input type TTL-Compatible CMOS Output type Push-Pull Features Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs Rating Catalog
Technology Family AHCT Supply voltage (Min) (V) 4.5 Supply voltage (Max) (V) 5.5 Number of channels (#) 8 IOL (Max) (mA) 8 IOH (Max) (mA) -8 ICC (Max) (uA) 40 Input type TTL-Compatible CMOS Output type Push-Pull Features Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs Rating Catalog
PDIP (N) 20 229 mm² 24.33 x 9.4 SOIC (DW) 20 132 mm² 12.8 x 10.3 SOP (NS) 20 98 mm² 12.6 x 7.8 SSOP (DB) 20 38 mm² 5.3 x 7.2 TSSOP (PW) 20 29 mm² 4.4 x 6.5
  • Inputs are TTL-Voltage Compatible
  • Latch-Up Performance Exceeds 250 mA
    Per JESD 17
  • On Products Compliant to MIL-PRF-38535,
    All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters.
  • Inputs are TTL-Voltage Compatible
  • Latch-Up Performance Exceeds 250 mA
    Per JESD 17
  • On Products Compliant to MIL-PRF-38535,
    All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters.

The SNx4AHCT240 octal buffers/drivers are designed specifically to improve both the performance and density of tri-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.

The SNx4AHCT240 octal buffers/drivers are designed specifically to improve both the performance and density of tri-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.

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Technical documentation

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Type Title Date
* Data sheet SNx4AHCT240 Octal Inverting Buffers/Drivers With Tri-State Outputs datasheet (Rev. N) PDF | HTML 06 Feb 2018
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
More literature Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
Application note Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) 02 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Design guide AHC/AHCT Designer's Guide February 2000 (Rev. D) 24 Feb 2000
More literature Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) 01 Apr 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Live Insertion 01 Oct 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

User guide: PDF | HTML
Not available on TI.com
Simulation model

SN74AHCT240 Behavioral SPICE Model

SLCM006.ZIP (7 KB) - PSpice Model
Package Pins Download
PDIP (N) 20 View options
SO (NS) 20 View options
SOIC (DW) 20 View options
SSOP (DB) 20 View options
TSSOP (PW) 20 View options

Ordering & quality

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