16-Bit 2.5-V to 3.3-V/3.3-V To 5-V Level Shifting Transceiver With 3-State Outputs

SN74ALVC164245

ACTIVE

Product details

Technology Family ALVC Bits (#) 16 High input voltage (Min) (Vih) 1.7 High input voltage (Max) (Vih) 5.5 Vout (Min) (V) 2.3 Vout (Max) (V) 5.5 IOH (Max) (mA) -24 IOL (Max) (mA) 24 Rating Catalog
Technology Family ALVC Bits (#) 16 High input voltage (Min) (Vih) 1.7 High input voltage (Max) (Vih) 5.5 Vout (Min) (V) 2.3 Vout (Max) (V) 5.5 IOH (Max) (mA) -24 IOL (Max) (mA) 24 Rating Catalog
SSOP (DL) 48 164 mm² 15.88 x 10.35 TSSOP (DGG) 48 101 mm² 12.5 x 8.1
  • Member of the Texas Instruments Widebus™ Family
  • Maximum tpd of 5.8 ns at 3.3 V
  • ±24-mA Output Drive at 3.3 V
  • Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • APPLICATIONS
    • Electronic Points of Sale
    • Printers and Other Peripherals
    • Motor Drives
    • Wireless and Telecom Infrastructures
    • Wearable Health and Fitness Devices

All other trademarks are the property of their respective owners

  • Member of the Texas Instruments Widebus™ Family
  • Maximum tpd of 5.8 ns at 3.3 V
  • ±24-mA Output Drive at 3.3 V
  • Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • APPLICATIONS
    • Electronic Points of Sale
    • Printers and Other Peripherals
    • Motor Drives
    • Wireless and Telecom Infrastructures
    • Wearable Health and Fitness Devices

All other trademarks are the property of their respective owners

This 16-bit (dual-octal) noninverting bus transceiver contains two separate supply rails. B port has VCCB, which is set to operate at 3.3 V and 5 V. A port has VCCA, which is set to operate at 2.5 V and 3.3 V. This allows for translation from a 2.5-V to a 3.3-V environment, and vice versa, or from a 3.3-V to a 5-V environment, and vice versa.

The SN74ALVC164245 is designed for asynchronous communication between data buses. The control circuitry (1DIR, 2DIR, 1OE, and 2OE) is powered by VCCA.

To ensure the high-impedance state during power up or power down, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

This 16-bit (dual-octal) noninverting bus transceiver contains two separate supply rails. B port has VCCB, which is set to operate at 3.3 V and 5 V. A port has VCCA, which is set to operate at 2.5 V and 3.3 V. This allows for translation from a 2.5-V to a 3.3-V environment, and vice versa, or from a 3.3-V to a 5-V environment, and vice versa.

The SN74ALVC164245 is designed for asynchronous communication between data buses. The control circuitry (1DIR, 2DIR, 1OE, and 2OE) is powered by VCCA.

To ensure the high-impedance state during power up or power down, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

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Technical documentation

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Type Title Date
* Data sheet SN74ALVC164245 16-Bit 2.5-V to 3.3-V or 3.3-V to 5-V Level-Shifting Transceiver With 3-State Outputs datasheet (Rev. Q) 27 Sep 2016
Selection guide Voltage Translation Buying Guide (Rev. A) 15 Apr 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
User guide ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B) 01 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) 08 Sep 1999
Application note TI SN74ALVC16835 Component Specification Analysis for PC100 03 Aug 1998
Application note Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A) 13 May 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

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Simulation model

SN74ALVC164245 IBIS Model (Rev. C)

SCEM026C.ZIP (58 KB) - IBIS Model
Package Pins Download
SSOP (DL) 48 View options
TSSOP (DGG) 48 View options

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