Product details

Technology Family ALVC Supply voltage (Min) (V) 1.65 Supply voltage (Max) (V) 3.6 Number of channels (#) 8 IOL (Max) (mA) 24 ICC (Max) (uA) 10 IOH (Max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs Rating Catalog
Technology Family ALVC Supply voltage (Min) (V) 1.65 Supply voltage (Max) (V) 3.6 Number of channels (#) 8 IOL (Max) (mA) 24 ICC (Max) (uA) 10 IOH (Max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs Rating Catalog
SOIC (DW) 20 132 mm² 12.8 x 10.3 SOP (NS) 20 98 mm² 12.6 x 7.8 TSSOP (PW) 20 29 mm² 4.4 x 6.5 TVSOP (DGV) 20 32 mm² 5 x 6.4 VQFN (RGY) 20 16 mm² 3.5 x 4.5
  • Operates From 1.65 V to 3.6 V
  • Max tpd of 2.8 ns at 3.3 V
  • ±24-mA Output Drive at 3.3 V
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

  • Operates From 1.65 V to 3.6 V
  • Max tpd of 2.8 ns at 3.3 V
  • ±24-mA Output Drive at 3.3 V
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

This octal buffer/line driver is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVC244 is organized as two 4-bit line drivers with separate output-enable (OE)\ inputs. When OE\ is low, the device passes data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This octal buffer/line driver is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVC244 is organized as two 4-bit line drivers with separate output-enable (OE)\ inputs. When OE\ is low, the device passes data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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Technical documentation

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Type Title Date
* Data sheet SN74ALVC244 datasheet (Rev. G) 31 Aug 2004
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
User guide ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B) 01 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) 08 Sep 1999
Application note TI SN74ALVC16835 Component Specification Analysis for PC100 03 Aug 1998
Application note Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A) 13 May 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

User guide: PDF | HTML
Not available on TI.com
Evaluation board

14-24-NL-LOGIC-EVM — Generic 14 through 24 pin non-leaded package evaluation module

Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
User guide: PDF | HTML
Not available on TI.com
Daughter card

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TMDSCNCD280049C is an HSEC180 controlCARD based evaluation and development tool for the C2000™ F28004x series of microcontroller products. controlCARDs are ideal to use for initial evaluation and system prototyping. controlCARDs are complete board-level modules that utilize one of two standard form (...)

User guide: PDF | HTML
Daughter card

TMDSCNCD28379D — F28379D controlCARD for C2000 Real time control development kits

TMDSCNCD28379D is an HSEC180 controlCARD based evaluation and development tool for the F2837xD,  F2837xS, and F2807x series in the TI MCU. controlCARDs are ideal to use for initial evaluation and system prototyping. controlCARDs are complete board-level modules that utilize one of two standard (...)

User guide: PDF | HTML
Not available on TI.com
Development kit

TMDSDOCK28379D — F28379D Delfino Experimenter Kit

TMDSDOCK28379D is a HSEC180 controlCARD based evaluation and development tool for the C2000™ Delfino™ F2837x and Piccolo F2807x series of microcontroller products. The Docking Station provides power to the controlCARD and has a bread-board area for prototyping. Access to the key device (...)

User guide: PDF | HTML
Not available on TI.com
Simulation model

SN74ALVC244 IBIS Model (Rev. A)

SCEM386A.ZIP (45 KB) - IBIS Model
Simulation model

SN74ALVC244 Behavioral SPICE Model

SCEM761.ZIP (7 KB) - PSpice Model
Reference designs

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This reference design is a 4-kW interleaved CCM totem pole (TTPL) bridgeless PFC reference design using a 64-pin C2000™ microcontroller, LM3410 gallium nitride device and TMCS1100 hall sensor. It is based on TIDM-02008 bidirectional interleaved CCM TTPL bridgeless PFC reference (...)
Schematic: PDF
Reference designs

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The DesignDRIVE Development Kit is a reference design for a complete industrial drive directly connecting to a three phase ACI or PMSM motor. Many drive topologies can be created from the combined control, power and communications technologies included on this single platform.  Includes (...)
User guide: PDF
Schematic: PDF
Reference designs

TIDM-TM4C129CAMERA — Camera Reference Design for ARM® Cortex®-M Microcontrollers (MCUs)

This design implements a network camera with a QVGA display panel and an embedded web server for remote monitoring.  With a memory footrpint of 250KB for the web server, there is ample memory available on the TM4C129x microcontroller for additional customizations.
Schematic: PDF
Package Pins Download
SO (NS) 20 View options
SOIC (DW) 20 View options
TSSOP (PW) 20 View options
TVSOP (DGV) 20 View options
VQFN (RGY) 20 View options

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