SN74ALVCH162268

ACTIVE

12-bit to 24-bit registered bus exchanger with 3-state outputs

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12-bit to 24-bit registered bus exchanger with 3-state outputs

SN74ALVCH162268

ACTIVE

Product details

Parameters

Technology Family ALVC Supply voltage (Min) (V) 1.65 Supply voltage (Max) (V) 3.6 Number of channels (#) 24 IOL (Max) (mA) 24 IOH (Max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Damping resistors, Bus-hold Data rate (Max) (Mbps) 300 Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other Universal bus exchanger (UBE)

Package | Pins | Size

SSOP (DL) 56 191 mm² 18.42 x 10.35 TSSOP (DGG) 56 113 mm² 14 x 8.1 open-in-new Find other Universal bus exchanger (UBE)

Features

  • Member of the Texas Instruments Widebus™ Family
  • Operates From 1.65 V to 3.6 V VCC
  • Max tpd of 4.8 ns at 3.3 V VCC
  • ±24 mA Output Drive at 3.3 V VCC
  • B-Port Outputs Have Equivalent 26- Series Resistors, So No External Resistors Are Required
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

Widebus is a trademark of Texas Instruments.

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Description

This 12-bit to 24-bit registered bus exchanger is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH162268 is used for applications in which data must be transferred from a narrow high-speed bus to a wide, lower-frequency bus.

The device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input when the appropriate clock-enable (CLKEN)\ inputs are low. The select (SEL)\ line is synchronous with CLK and selects 1B or 2B input data for the A outputs.

For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of these inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables (OEA\, OEB\). These control terminals are registered, so bus direction changes are synchronous with CLK.

The B outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible and OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Due to OE\ being routed through a register, the active state of the outputs cannot be determined prior to the arrival of the first clock pulse.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

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Technical documentation

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Type Title Date
* Data sheet SN74ALVCH162268 datasheet (Rev. L) Sep. 22, 2004
Application note An Overview of Bus-Hold Circuit and the Applications (Rev. B) Sep. 17, 2018
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
User guide ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B) Aug. 01, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) May 22, 2002
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) Sep. 08, 1999
Application note TI SN74ALVC16835 Component Specification Analysis for PC100 Aug. 03, 1998
Application note Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A) May 13, 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996
Application note Understanding Advanced Bus-Interface Products Design Guide May 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Design tools & simulation

SIMULATION MODEL Download
SCEM154.ZIP (49 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
SSOP (DL) 56 View options
TSSOP (DGG) 56 View options

Ordering & quality

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