SN74ALVCH16863

ACTIVE

18-Bit Transceiver With 3-State Outputs

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18-Bit Transceiver With 3-State Outputs

SN74ALVCH16863

ACTIVE

Product details

Parameters

Technology Family ALVC VCC (Min) (V) 1.65 VCC (Max) (V) 3.6 Bits (#) 18 IOL (Max) (mA) 24 IOH (Max) (mA) -24 Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other Standard transceiver

Package | Pins | Size

TSSOP (DGG) 56 113 mm² 14 x 8.1 open-in-new Find other Standard transceiver

Features

  • Member of the Texas Instruments WidebusTM Family
  • EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

    EPIC and Widebus are trademarks of Texas Instruments Incorporated.

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Description

This 18-bit bus transceiver is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH16863 is an 18-bit noninverting transceiver designed for synchronous communication between data buses. The control-function implementation minimizes external timing requirements.

The SN74ALVCH16863 can be used as two 9-bit transceivers or one 18-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the output-enable (OEAB\ or OEBA\) inputs.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH16863 is characterized for operation from -40°C to 85°C.

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Technical documentation

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Type Title Date
* Data sheet 18-Bit Transceiver With 3-State Outputs datasheet (Rev. B) Feb. 11, 1999
Application note An Overview of Bus-Hold Circuit and the Applications (Rev. B) Sep. 17, 2018
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
User guide ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B) Aug. 01, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) May 22, 2002
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) Sep. 08, 1999
Application note TI SN74ALVC16835 Component Specification Analysis for PC100 Aug. 03, 1998
Application note Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A) May 13, 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996
Application note Understanding Advanced Bus-Interface Products Design Guide May 01, 1996

Design & development

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CAD/CAE symbols

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TSSOP (DGG) 56 View options

Ordering & quality

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