Product details

Technology Family AUP Supply voltage (Min) (V) 0.8 Supply voltage (Max) (V) 3.6 Number of channels (#) 2 IOL (Max) (mA) 4 ICC (Max) (uA) 0.9 IOH (Max) (mA) 0 Input type Standard CMOS Output type Open-Drain Features Very high speed (tpd 5-10ns), Partial power down (Ioff), Over-voltage tolerant inputs Rating Catalog
Technology Family AUP Supply voltage (Min) (V) 0.8 Supply voltage (Max) (V) 3.6 Number of channels (#) 2 IOL (Max) (mA) 4 ICC (Max) (uA) 0.9 IOH (Max) (mA) 0 Input type Standard CMOS Output type Open-Drain Features Very high speed (tpd 5-10ns), Partial power down (Ioff), Over-voltage tolerant inputs Rating Catalog
DSBGA (YFP) 6 1 mm² .8 x 1.2 SOT-SC70 (DCK) 6 4 mm² 2 x 2.1 USON (DRY) 6 1 mm² 1.5 x 1 X2SON (DSF) 6 1 mm² 1 x 1
  • Low static-power consumption (ICC = 0.9 µA maximum)
  • Low dynamic-power consumption (Cpd = 1 pF typical at 3.3 V)
  • Low input capacitance (Ci = 1.5 pF typical)
  • Low noise – overshoot and undershoot <10% of VCC
  • Ioff supports live insertion, partial-power-down mode, and back-drive protection
  • Input hysteresis allows slow input transition and better switching noise immunity at the input (Vhys = 250 mV typical at 3.3 V)
  • Wide operating VCC range of 0.8 V to 3.6 V
  • Optimized for 3.3 V operation
  • 3.6-V I/O tolerant to support mixed-mode signal operation
  • tpd = 3.3 ns maximum at 3.3 V
  • Suitable for point-to-point applications
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • ESD performance tested per JESD 22
    • 4500-V human-body model
    • 1500-V charged-device model
  • Low static-power consumption (ICC = 0.9 µA maximum)
  • Low dynamic-power consumption (Cpd = 1 pF typical at 3.3 V)
  • Low input capacitance (Ci = 1.5 pF typical)
  • Low noise – overshoot and undershoot <10% of VCC
  • Ioff supports live insertion, partial-power-down mode, and back-drive protection
  • Input hysteresis allows slow input transition and better switching noise immunity at the input (Vhys = 250 mV typical at 3.3 V)
  • Wide operating VCC range of 0.8 V to 3.6 V
  • Optimized for 3.3 V operation
  • 3.6-V I/O tolerant to support mixed-mode signal operation
  • tpd = 3.3 ns maximum at 3.3 V
  • Suitable for point-to-point applications
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • ESD performance tested per JESD 22
    • 4500-V human-body model
    • 1500-V charged-device model

The SN74AUP2G07 device is a dual buffer gate with open drain output that operates from 0.8 V to 3.6 V.

The SN74AUP2G07 device is a dual buffer gate with open drain output that operates from 0.8 V to 3.6 V.

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Technical documentation

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Type Title Date
* Data sheet SN74AUP2G07 Low-Power Dual Buffer/Driver With Open-Drain Outputs datasheet (Rev. E) 04 Oct 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding Schmitt Triggers 21 Sep 2011
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic EVM supporting 5 through 8 pin DCK, DCT, DCU, DRL, and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
Not available on TI.com
Simulation model

SN74AUP2G07 PSpice Model

SCEM577.ZIP (50 KB) - PSpice Model
Simulation model

SN74AUP2G07 Behavioral SPICE Model

SCEM677.ZIP (7 KB) - PSpice Model
Package Pins Download
DSBGA (YFP) 6 View options
SC70 (DCK) 6 View options
SON (DRY) 6 View options
SON (DSF) 6 View options

Ordering & quality

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