SN74AVCB164245

ACTIVE

16-Bit Dual-Supply Bus Transceiver w/ Config. Xlation and 3-State Outputs

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16-Bit Dual-Supply Bus Transceiver w/ Config. Xlation and 3-State Outputs

SN74AVCB164245

ACTIVE

Product details

Parameters

Technology Family AVC Bits (#) 16 High input voltage (Min) (Vih) 0.91 High input voltage (Max) (Vih) 3.6 Output voltage (Min) (V) 1.4 Output voltage (Max) (V) 3.6 IOH (Max) (mA) -12 IOL (Max) (mA) 12 Rating Catalog open-in-new Find other Direction-controlled voltage translators

Package | Pins | Size

TSSOP (DGG) 48 101 mm² 12.5 x 8.1 TVSOP (DGV) 48 62 mm² 9.7 x 6.4 open-in-new Find other Direction-controlled voltage translators

Features

  • Member of the Texas Instruments Widebus™ Family
  • DOC™ Circuitry Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation
  • Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of ±24 mA at 2.5-V VCC
  • Control Inputs VIH/VIL Levels Are Referenced to VCCB Voltage
  • If Either VCC Input Is at GND, Both Ports Are in the High-Impedance State
  • Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
  • Ioff Supports Partial-Power-Down Mode Operation
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over Full 1.4-V to 3.6-V Power-Supply Range
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus, DOC are trademarks of Texas Instruments.

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Description

This 16-bit (dual-octal) noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.4 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.4 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVCB164245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are effectively isolated.

The SN74AVCB164245 is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCB.

To ensure the high-impedance state during power up or power down, OE should be tied to VCCB through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. If either VCC input is at GND, both ports are in the high-impedance state.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet SN74AVCB164245 datasheet (Rev. D) May 31, 2005
Selection guides Voltage translation buying guide Jun. 13, 2019
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application notes Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) Apr. 30, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. A) Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
More literature LCD Module Interface Application Clip May 09, 2003
User guides AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) Aug. 20, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
Application notes 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) May 22, 2002
Application notes Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) Jul. 07, 1999
Application notes AVC Logic Family Technology and Applications (Rev. A) Aug. 26, 1998

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

DEVELOPMENT KITS Download
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Features
  • 66AK2G02 C66x DSP+ARM A15 Processor at 600MHz
  • 2-GByte DDR3L with ECC
  • TPS659118 PMIC
  • Audio and Serial expansion headers
  • Processor SDK Linux and TI-RTOS support
  • Supports Gigabit Ethernet
DEVELOPMENT KITS Download
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The EVMK2GX (also known as "K2G") 1GHz Evaluation Module (EVM) enables developers to immediately start evaluating the 66AK2Gx processor family, and to accelerate the development of audio, industrial motor control, smart grid protection and other high reliability, real-time compute intensive (...)

Features
  • 66AK2G12 C66x DSP+ARM A15 Processor at 1GHz
  • 2-GByte DDR3L with ECC
  • TPS65911A PMIC
  • Audio and serial expansion headers
  • Processor SDK Linux and TI-RTOS support
DEVELOPMENT KITS Download
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Description

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Features
  • 66AK2G12 C66x DSP+ARM A15 Processor at 1GHz
  • 2-GByte DDR3L with ECC
  • TPS65911A PMIC
  • Audio and serial expansion headers
  • Processor SDK Linux and TI-RTOS support

Design tools & simulation

SIMULATION MODELS Download
SCEJ158.ZIP (59 KB) - HSpice Model
SIMULATION MODELS Download
SCEM483A.ZIP (52 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
BGA MICROSTAR JUNIOR (ZQL) 56 View options
BGA MICROSTAR JUNIOR (ZRD) 54 View options
TSSOP (DGG) 48 View options
TVSOP (DGV) 48 View options

Ordering & quality

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