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8-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation and 3-State Outputs

SN74AVCH8T245

ACTIVE

Product details

Parameters

Technology Family AVC Bits (#) 8 High input voltage (Min) (Vih) 1.2 High input voltage (Max) (Vih) 3.6 Output voltage (Min) (V) 1.2 Output voltage (Max) (V) 3.6 IOH (Max) (mA) -12 IOL (Max) (mA) 12 Rating Catalog open-in-new Find other Direction-controlled voltage translators

Package | Pins | Size

TSSOP (PW) 24 34 mm² 4.4 x 7.8 TVSOP (DGV) 24 32 mm² 5 x 6.4 VQFN (RHL) 24 19 mm² 3.5 x 5.5 open-in-new Find other Direction-controlled voltage translators

Features

  • Control Inputs (DIR and OE) VIH and VIL Levels Are Referenced to VCCA Voltage
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup or Pulldown Resistors
  • VCC Isolation Feature
  • Fully Configurable Dual-Rail Design
  • I/Os Are 4.6-V Tolerant
  • Ioff Supports Partial-Power-Down Mode Operation
  • Max Data Rates:
    • 320 Mbps (VCCA ≥ 1.8 V and VCCB ≥ 1.8 V)
    • 170 Mbps (VCCA ≤ 1.8 V or VCCB ≤ 1.8 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 8000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
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Description

The SN74AVCH8T245 is an 8-bit noninverting bus transceiver that uses two separate configurable power-supply rails. The A port is designed to track VCCA, which accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB, which also accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVCH8T245 is designed for asynchronous communication between data buses. The device transmits data from either the A bus to the B bus, or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are effectively isolated.

The SN74AVCH8T245 is designed so that the control pins (DIR and OE) are referenced to VCCA.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device.

The VCC isolation feature ensures that if either VCCA or VCCB is at GND, then the outputs are in the high-impedance state. The bus-hold circuitry on the powered-up side always stays active.

The SN74AVCH8T245 solution is compatible with a single-supply system and can be replaced later with a ’245 function, with minimal printed circuit board redesign.

To ensure the high-impedance state during power up or power down, OE shall be tied to VCCA through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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Technical documentation

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Type Title Date
* Datasheet SN74AVCH8T245 8-Bit Dual-Supply Bus Transceiver With Configurable Level-Shifting, Voltage Translation, and 3-State Outputs datasheet (Rev. H) Apr. 01, 2016
Solution guides Voltage translation buying guide Jun. 13, 2019
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application notes Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) Apr. 30, 2015
Solution guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. A) Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
More literature LCD Module Interface Application Clip May 09, 2003
User guides AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) Aug. 20, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
Application notes 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) May 22, 2002
Application notes Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) Jul. 07, 1999
Application notes AVC Logic Family Technology and Applications (Rev. A) Aug. 26, 1998

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices
EVALUATION BOARDS Download
document-generic User guide
$20.00
Description

The generic EVM is designed to support one, two, four and eight channel LVC and AVC direction-controlled translation devices. It also supports the bus hold and automotive -Q1 devices in the same number of channels. The AVC are low voltage translation devices with lower drive strength of 12mA. LVC is (...)

Features
  • SMB connector available for high speed operation
  • Ground port available on each header pin to maintain signal integrity
  • DIR and OE have 10K ohm pull up /pull down resistor options
  • Designed to support up to 20 different devices

Design tools & simulation

SIMULATION MODELS Download
SCEM426.ZIP (68 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
TSSOP (PW) 24 View options
TVSOP (DGV) 24 View options
VQFN (RHL) 24 View options

Ordering & quality

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Videos

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Posted: 21-Jan-2019
Duration: 01:57

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