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3.3-V, 1:1 (SPST), 8-channel FET bus switch with level shifter

SN74CB3T3245

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Product details

Parameters

Configuration 1:1 SPST Number of channels (#) 8 Power supply voltage - single (V) 2.5, 3.3 Ron (Typ) (Ohms) 5 ON-state leakage current (Max) (µA) 20 Bandwidth (MHz) 100 Operating temperature range (C) -40 to 85 Features Powered-off protection, Signal path translation Input/output continuous current (Max) (mA) 128 Rating Catalog CON (Typ) (pF) 5 open-in-new Find other Analog switches & muxes

Package | Pins | Size

SOIC (DW) 20 132 mm² 12.8 x 10.3 SSOP (DBQ) 20 52 mm² 8.65 x 6 TSSOP (PW) 20 42 mm² 6.5 x 6.4 TVSOP (DGV) 20 32 mm² 5 x 6.4 open-in-new Find other Analog switches & muxes

Features

  • Standard ’245-Type Pinout
  • Output Voltage Translation Tracks VCC
  • Supports Mixed-Mode Signal Operation on All Data I/O Ports
    • 5-V Input Down to 3.3-V Output Level Shift With 3.3-V VCC
    • 5-V/3.3-V Input Down to 2.5-V Output Level Shift With 2.5-V VCC
  • 5-V-Tolerant I/Os With Device Powered Up or Powered Down
  • Bidirectional Data Flow With Near-Zero Propagation Delay
  • Low ON-State Resistance (ron) Characteristics (ron = 5 Ω Typical)
  • Low Input/Output Capacitance Minimizes Loading (Cio(OFF) = 5 pF Typical)
  • Data and Control Inputs Provide Undershoot Clamp Diodes
  • Low Power Consumption (ICC = 40 µA Maximum)
  • VCC Operating Range From 2.3 V to 3.6 V
  • Data I/Os Support 0- to 5-V Signaling Levels
    (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
  • Control Inputs Can Be Driven by TTL or
    5-V/3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Ideal for Low-Power Portable Equipment

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Description

The SN74CB3T3245 device is a high-speed TTL-compatible 8-bit FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC.

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Technical documentation

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Type Title Date
* Data sheet SN74CB3T3245 8-Bit FET Bus Switch 2.5-V and 3.3-V Low-Voltage With 5-V-Tolerant Level Shifter datasheet (Rev. C) May 31, 2018
Application note Multiplexers and Signal Switches Glossary (Rev. A) Jun. 09, 2021
Application note CBT-C, CB3T, and CB3Q Signal-Switch Families (Rev. B) Jun. 08, 2021
Application note Eliminate Power Sequencing with Powered-off Protection Signal Switches (Rev. C) Jan. 06, 2021
Application note Selecting the Right Texas Instruments Signal Switch (Rev. B) Apr. 02, 2020
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note How to Select Little Logic (Rev. A) Jul. 26, 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
More literature Digital Bus Switch Selection Guide (Rev. A) Nov. 10, 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application note Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
User guide Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note Bus FET Switch Solutions for Live Insertion Applications Feb. 07, 2003

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

INTERFACE ADAPTER Download
document-generic User guide
10
Description

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

Features
  • Quick testing of TI's leaded surface mount packages 
  • Allows leaded suface mount packages to be plugged into 100mil spaced bread board 
  • Supports TI's 8 most popular leaded packages with a single panel


Design tools & simulation

SIMULATION MODEL Download
SCDJ028.ZIP (99 KB) - HSpice Model
SIMULATION MODEL Download
SCDM055.ZIP (26 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
SOIC (DW) 20 View options
SSOP (DBQ) 20 View options
TSSOP (PW) 20 View options
TVSOP (DGV) 20 View options

Ordering & quality

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  • MSL rating/Peak reflow
  • MTBF/FIT estimates
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  • Qualification summary
  • Ongoing reliability monitoring

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