SN74HC125-Q1

ACTIVE

Automotive Catalog Quadruple Bus Buffer Gates With 3-State Outputs

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Automotive Catalog Quadruple Bus Buffer Gates With 3-State Outputs

SN74HC125-Q1

ACTIVE

Product details

Parameters

Technology Family HC VCC (Min) (V) 2 VCC (Max) (V) 6 Channels (#) 4 IOL (Max) (mA) 6 ICC (Max) (uA) 16 IOH (Max) (mA) -6 Input type Standard CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Input clamp diode Data rate (Mbps) 56 Rating Automotive open-in-new Find other Non-Inverting buffer/driver

Package | Pins | Size

TSSOP (PW) 14 32 mm² 5 x 6.4 open-in-new Find other Non-Inverting buffer/driver

Features

  • AEC-Q100 Qualified for automotive applications:
    • Device temperature grade 1:
      –40°C to +125°C, TA
  • Buffered inputs
  • Positive and negative input clamp diodes
  • Wide operating voltage range: 2 V to 6 V
  • Supports fanout up to 10 LSTTL loads
  • Significant power reduction compared to LSTTL logic ICs

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open-in-new Find other Non-Inverting buffer/driver

Description

This device contains four independent buffers with 3-state outputs. Each gate performs the Boolean function Y = A in positive logic.

open-in-new Find other Non-Inverting buffer/driver
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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet SN74HC125-Q1 Automotive Quadruple Buffers with 3-State Outputs datasheet (Rev. B) Apr. 14, 2020
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
More literature Automotive Logic Devices Brochure Aug. 27, 2014
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application notes Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
TSSOP (PW) 14 View options

Ordering & quality

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