Product details

Technology Family LS Supply voltage (Min) (V) 4.75 Supply voltage (Max) (V) 5.25 Number of channels (#) 4 Inputs per channel 2 IOL (Max) (mA) 8 IOH (Max) (mA) -0.4 Input type Bipolar Output type Push-Pull Features High speed (tpd 10- 50ns) Data rate (Max) (Mbps) 35 Rating Catalog
Technology Family LS Supply voltage (Min) (V) 4.75 Supply voltage (Max) (V) 5.25 Number of channels (#) 4 Inputs per channel 2 IOL (Max) (mA) 8 IOH (Max) (mA) -0.4 Input type Bipolar Output type Push-Pull Features High speed (tpd 10- 50ns) Data rate (Max) (Mbps) 35 Rating Catalog
PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 SOP (PS) 8 48 mm² 6.2 x 7.8 SSOP (DB) 14 48 mm² 6.2 x 7.8
  • Package Options Include:
    • Plastic Small-Outline (D, NS, PS)
    • Shrink Small-Outline (DB)
    • Ceramic Flat (W)
    • Ceramic Chip Carriers (FK)
    • Standard Plastic (N)
    • Ceramic (J)
  • Also Available as Dual 2-Input Positive-NAND Gate in Small-Outline (PS) Package
  • Inputs Are TTL Compliant; VIH = 2 V and
    VIL = 0.8 V
  • Inputs Can Accept 3.3-V or 2.5-V Logic Inputs
  • SN5400, SN54LS00, and SN54S00 are Characterized For Operation Over the Full Military Temperature Range of –55ºC to 125ºC
  • Package Options Include:
    • Plastic Small-Outline (D, NS, PS)
    • Shrink Small-Outline (DB)
    • Ceramic Flat (W)
    • Ceramic Chip Carriers (FK)
    • Standard Plastic (N)
    • Ceramic (J)
  • Also Available as Dual 2-Input Positive-NAND Gate in Small-Outline (PS) Package
  • Inputs Are TTL Compliant; VIH = 2 V and
    VIL = 0.8 V
  • Inputs Can Accept 3.3-V or 2.5-V Logic Inputs
  • SN5400, SN54LS00, and SN54S00 are Characterized For Operation Over the Full Military Temperature Range of –55ºC to 125ºC

The SNx4xx00 devices contain four independent,
2-input NAND gates. The devices perform the Boolean function Y = A .B or Y = A + B in positive logic.

The SNx4xx00 devices contain four independent,
2-input NAND gates. The devices perform the Boolean function Y = A .B or Y = A + B in positive logic.

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Technical documentation

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Type Title Date
* Data sheet SNx400, SNx4LS00, and SNx4S00 Quadruple 2-Input Positive-NAND Gates datasheet (Rev. D) 19 May 2017
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Designing with the SN54/74LS123 (Rev. A) 01 Mar 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

In stock
Limit: 5
Simulation model

SN74LS00 IBIS Model (Rev. B)

SDLM003B.ZIP (7 KB) - IBIS Model
Simulation model

SN74LS00 Behavioral SPICE Model

SDLM060.ZIP (7 KB) - PSpice Model
Package Pins Download
PDIP (N) 14 View options
SO (NS) 14 View options
SO (PS) 8 View options
SOIC (D) 14 View options
SSOP (DB) 14 View options

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