SN74LS09

ACTIVE

Quad 2-input positive-AND gates with open collector outputs

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Product details

Parameters

Technology Family LS VCC (Min) (V) 4.75 VCC (Max) (V) 5.25 Channels (#) 4 Inputs per channel 2 IOL (Max) (mA) 8 IOH (Max) (mA) 0 Input type Bipolar Output type Open-Collector Features High Speed (tpd 10-50ns) Data rate (Max) (Mbps) 35 Rating Catalog Operating temperature range (C) 0 to 70 open-in-new Find other AND gate

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 open-in-new Find other AND gate

Features

  • Package Options Include Plastic “Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPS
  • Dependable Texas Instruments Quality and Reliability

 

open-in-new Find other AND gate

Description

These devices contain four independent 2-input AND gates. The open-collector outputs require pull-up resistors to perform correctly. They may be connected to other open-collector outputs to implement active-low wired-OR or active-high wired-AND functions. Open-collector devices are often used to generate higher VOH levels.

The SN5409, SN54LS09, and SN54S09 are characterized for operation over the full military temperature range of -55°C to 125°C, The SN7409, SN74LS09, and SN74S09 are characterized for operation from 0°C to 70°C.

 

open-in-new Find other AND gate
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Technical documentation

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Type Title Date
* Datasheet Quadruple 2-Input Positive-AND Gates With Open-Collector Outputs datasheet Mar. 01, 1988
Technical articles How to keep your motor running safely Jun. 04, 2020
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Designing with the SN54/74LS123 (Rev. A) Mar. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODELS Download
SDLM052.ZIP (6 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SO (NS) 14 View options
SOIC (D) 14 View options

Ordering & quality

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